Circuitry for retiming a received data signal

Details Circuitry for retiming a received data signal Circuitry for retiming a received data signal

1996-10-10

1999-07-27

Chin, Stephen

Pulse or digital communications

Synchronizers

375371, 326 96, 327161, H04L 700

Patent

active

059303115

ABSTRACT:
A circuitry (10) is provided for automatically retiming a received synchronous data signal to a local clock. The circuitry (10) includes a first flip-flop (20) operable to register at least one synchronous data signal in response to a receive clock signal and to generate at least one data output signal. An OR gate (26) receives a data latch enable signal and a local clock signal. The local clock signal is frequency coherent with the receive clock signal. The OR gate (26) produces an enable signal. A latch (28) is coupled to the OR gate (26) for receiving the enable signal and in cascading arrangement with the first flip-flop (20). The latch (28) latches the data output signal on the falling edge of the local clock signal when the data latch enable signal is low. The latch (28) holds the latched data output signal as long as the local clock signal and the data latch enable signal are low. When either the local clock signal or the data latch enable signal is high, the latch (28) passes the data output signal. A second flip-flop (30), coupled in cascading arrangement with the latch (28), registers the data output signal passed through the latch (28) in response to the local clock signal. The signal output by the second flip-flop (30) is timed to the local clock signal.

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patent: 5504751 (1996-04-01), Ledzius et al.
patent: 5515403 (1996-05-01), Sloan et al.

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