Circuitry for resetting an electrically erasable memory device

Details Circuitry for resetting an electrically erasable memory device Circuitry for resetting an electrically erasable memory device

1996-03-22

1997-06-10

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518523, 365226, 365228, G11C 1602

Patent

active

056383258

ABSTRACT:
When power is turned off during erasure or writing, electric charge is left due to high voltage. This charge is discharged when the power is turned on. Thus, erroneous erasure, erroneous writing, and erroneous reading are prevented. It comprises a reset circuit 2 for producing a reset signal when the power is turned on, a bias circuit 3 for producing a given voltage during the period of the reset signal, a driver 4 for selecting and driving all word lines with a given voltage during the period of the reset signal, and discharging circuits 5 for electrically discharging all control lines and all bit lines during the period of the reset signal.

REFERENCES:
patent: 4905197 (1990-02-01), Urai
patent: 5138575 (1992-08-01), Ema et al.

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