Circuitry for providing replica data transfer signal during DMA

Details Circuitry for providing replica data transfer signal during DMA Circuitry for providing replica data transfer signal during DMA

1993-12-07

1995-08-15

Robertson, David L.

Boots, shoes, and leggings

395500, 364DIG1, G06F 9455, G06F 1328

Patent

active

054427533

ABSTRACT:
The present invention includes two variations of an apparatus which generate a version of the IORC* bus signal that is supplied to the read strobe input of a floppy disk controller that is asserted at the appropriate time during verify cycles between the floppy disk controller and a DMA controller. These designs allow an 82077 floppy disk controller to operate properly in FIFO mode when it is being used with software that does not require generation of this signal. The designs include use of a PAL and certain bus signal inputs to generate a signal which is asserted at the appropriate times during verify transfers. This signal is combined with the regular IORC* bus signal to produce the signal that is provided to the read strobe input of the floppy disk controller.

REFERENCES:
patent: 4371929 (1983-02-01), Brann et al.
patent: 4473879 (1984-09-01), Tachiuchi et al.
patent: 4481578 (1984-11-01), Hughes et al.
patent: 4527237 (1985-07-01), Frieder et al.
patent: 4530053 (1985-07-01), Kriz et al.
patent: 4989135 (1991-01-01), Miki
patent: 5056010 (1991-10-01), Huang
patent: 5062073 (1991-10-01), Masuda et al.
patent: 5307476 (1994-04-01), Waldrop et al.
Intel Corp., Microprocessor and Peripheral Handbook 1989, vol. 1, pp. 2-222 to 2-258.
Intel Corp., Microprocessor and Peripheral Handbook 1989, vol. 2, pp. 7-32 to 7-85.
NEC Electronics, Inc., Microcomputer Products, vol. 2, 1987, pp. 6-2 to 6-25.
Compaq Computer Corp., Compaq Deskpro 386/25 Technical Reference Guide, vol. 2, pp. 7-41 to 7-63.
IBM Technical Disclosure Bulletin, Diskette Verify Mode Operation Without DMA Controller Support, Nov. 1989.
IBM Technical Disclosure Bulletin, Time Sharing of System Data Bus During Storage Head Cycles, May 1986.

Affiliated with

Also associated with

Rating

Circuitry for providing replica data transfer signal during DMA does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuitry for providing replica data transfer signal during DMA , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuitry for providing replica data transfer signal during DMA will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2190169