Circuitry for preventing the use of erroneous data

Communications: electrical – Digital comparator systems

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214 164A, G06F 1100

Patent

active

039380815

ABSTRACT:
A transceiver for computer controlled stacker cranes comprising an interface which controls the voltage level of incoming and outgoing serial signals, a sampling circuit and a voting circuit which together prevents transmission of transient or improper signals received from the interface, shift registers converting incoming serial data to parallel data and also converting stored parallel data to outgoing serial data, a temporary storage memory which holds parallel data received from the shift registers until commanded by timing signals to output said data, an end of transmission decoder which senses the end of a data message and triggers certain timing signals, timing circuitry for clocking transfer of data to and from said memory, and circuitry for preventing simultaneous transmission and reception of data.

REFERENCES:
patent: 3356837 (1967-12-01), Raymond
patent: 3386081 (1968-05-01), Varsos
patent: 3396369 (1968-08-01), Brothman et al.
patent: 3562708 (1971-02-01), Verbarg et al.
patent: 3568147 (1971-03-01), Gilson
patent: 3593307 (1971-07-01), Gouge, Jr. et al.
patent: 3595412 (1971-07-01), Billingsley et al.
patent: 3646890 (1972-03-01), Snyder
patent: 3782565 (1974-01-01), Doran et al.

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