Circuitry for minimizing peak power in an amplifier carrying a p

Details Circuitry for minimizing peak power in an amplifier carrying a p Circuitry for minimizing peak power in an amplifier carrying a p

1992-10-20

1994-04-05

Mullins, James B.

Amplifiers

With control of power supply or bias voltage

With control of input electrode or gain control electrode bias

330124R, 330279, 330295, 455103, 455126, H03G 320

Patent

active

053008944

ABSTRACT:
In plural channel amplifier systems processing many phase locked signals of different frequencies as a combined signal, these signals may drift into a phase convergence causing a peak power occurrence in the amplifier which greatly exceeds the rated capacity of the amplifier system. Therefore, in accord with the invention, a dynamic adjustment system is provided to minimize the peak power to which the amplifier is subjected by adjusting the relative phase relationships of the many signals. The dynamic adjustment system includes a peak power detector, a hard wired logic decision circuit and a timing control to control phase shift adjustment steps.

REFERENCES:
patent: 4010426 (1977-03-01), Rambo
patent: 4064464 (1977-12-01), Morse
patent: 4370622 (1983-01-01), Hornbeck et al.
patent: 4546313 (1985-10-01), Moyer
patent: 5043673 (1991-08-01), Suematsu et al.
patent: 5101172 (1992-03-01), Ikeda et al.
patent: 5101211 (1992-03-01), DuFort

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