Circuitry for generating scalar products and sums of floating po

Details Circuitry for generating scalar products and sums of floating po Circuitry for generating scalar products and sums of floating po

1985-08-09

1986-11-11

Thomas, James D.

Boots, shoes, and leggings

364745, G06F 738

Patent

active

046226508

ABSTRACT:
Circuitry for generating scalar products and sums of floating point numbers with maximum accuracy and circuitry and a method for electronic computers by which scalar products of floating point numbers of the type pi, qi, ES(b,l,e1,e2) are summed with full precision in a fixed point representation by means of a summing unit (ALU) and one or more accumulator registers (ARC1, ARC2) with cells (Ai, j) for storing of codes of a base b having a length (2l+ 2 e1+ 2e2) for fixed point representation and certain overflow positions. By control means (SHR, E, Contr) the mantissas of products are delivered depending on the value of the respective exponents into the summing unit (ALU). By control means (RD, Contro), rounding operations ( .circle. , , .gradient., .increment.) demanded by the higher level computer are performed, and a rounded floating point number (.quadrature. c .epsilon. S(b,l,e1,e2)) and overflow (OF) and underflow (UF) criteria are delivered. Parallel, serial and word organized summing units (ALU) and accumulator registers (ACR) are usable and in another embodiment, the multiplication of the factors (pi, qi) is performed using a table of multiples store.

REFERENCES:
patent: 3388385 (1968-06-01), Lukes
patent: 3699326 (1972-10-01), Kindell et al.
patent: 3871578 (1975-03-01), Van De Goor et al.
patent: 4054787 (1977-10-01), Pos
patent: 4075704 (1978-02-01), O'Leary
patent: 4130879 (1978-12-01), Cushing
patent: 4135249 (1979-01-01), Irwin
patent: 4149261 (1979-04-01), Harigaya et al.
patent: 4229800 (1980-10-01), Gregorian et al.
patent: 4295203 (1981-10-01), Joyce
patent: 4338675 (1982-07-01), Palmer et al.
patent: 4409668 (1983-10-01), Yoshida
patent: 4429370 (1984-01-01), Blau et al.
patent: 4476537 (1984-10-01), Blau et al.
patent: 4490807 (1984-12-01), Chevillant et al.
patent: 4534010 (1985-08-01), Kobayashi et al.
Kuuth; The Art of Computer Programming, vol. 2; pp. 213-223, 1969.
Kulisch; "An Axiomatic Approach to Rounded Computations" Numer. Math., vol. 18; pp. 1-17; 1971.
Yohe; "Roundings in Floating-Point Arithmetic"; IEEE Trans. on Computers, vol. C-22, No. 6, pp. 577-589, Jun. 1973.
Sasao; "Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays"; IEEE Trans. on Computers, vol. C-30; No. 9, pp. 635-643, Sep. 1981.
Clegg; "Use of SPOOF's in the Analysis of Faulty Logic Networks" IEEE Trans. on Computers; vol. C-22, No. 3, pp. 229-234, Mar. 1973.
Bohlender; "Floating-Point Computation of Functions with Maximum Accuracy" IEEE Trans on Computers, vol. 26, No. 7, pp. 621-632 Jul. 1977.
Sproul "High-Speed Floating-Point Accumulator" IBM Technical Disclosure Bulletin, vol. 14, No. 10, pp. 2934-2936, Mar. 1972.

Affiliated with

Also associated with

Rating

Circuitry for generating scalar products and sums of floating po does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuitry for generating scalar products and sums of floating po, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuitry for generating scalar products and sums of floating po will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-380571