Circuitry for eliminating false lock in delay-locked loops

Details Circuitry for eliminating false lock in delay-locked loops Circuitry for eliminating false lock in delay-locked loops

2007-06-19

2007-06-19

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000

Reexamination Certificate

active

11169957

ABSTRACT:
A delay-locked loop (DLL) acquires correct lock when the delay line on the DLL delays a reference signal by one clock period. False lock occurs when the delay line delays the reference signal by more than one clock period. False lock may be detected by a false lock detector. The false lock detector may include (1) flip-flops to take samples of the delay line outputs and (2) combinational logic for detecting patterns in the samples that may indicate false lock. Once false lock has been detected, a hold circuit may ensure that false lock persists for at least the amount of time required by the DLL to acquire lock (i.e., to prevent reset of the DLL before it has acquired lock). After this determination is made, a reset generator may produce a reset signal for resetting the DLL.

REFERENCES:
patent: 6119242 (2000-09-01), Harrison
patent: 6452431 (2002-09-01), Waldrop
patent: 2006/0132205 (2006-06-01), Wu et al.

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