Electricity: motive power systems – Switched reluctance motor commutation control
Patent
1988-04-29
1990-02-06
Ro, Bentsu
Electricity: motive power systems
Switched reluctance motor commutation control
318138, 318480, H02P 602
Patent
active
048990930
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention concerns circuitry for electronically commutating a multiphase direct-current motor, whereby markers are distributed around the circumference of a rotor, the markers provide, in conjunction with a sensor, the commutating pulses that activate the motor's phase conductors, the pulses supplied by the sensor advance a counter that has output terminals, the output terminals control switches that switch the phase conductors alternately to operating and to reference voltage, and the counter re-zeroes itself after a certain number of pulses. Circuitry of this type is known. It is described for example in German OS No. 3 435 270. Its purpose is to activate the motor's various phase conductors at appropriate instants. The markers on the circumference of the rotor can be light-permeable or reflecting points that operate in conjunction with light-sensitive sensors or they can be permanent magnets that act on a sensor in the form of a Hall generator. The markers generate a periodic sequence of pulses that activate the phase conductors, which a counter cyclically connects by way of bipolar switches to either operating voltage or reference voltage. The sequence is constructed when the counter re-zeroes itself subsequent to a certain number of pulses that is a whole-number divisor of the number of markers.
Sometimes, however, the counter will re-zero itself a pulse too early or too late, preventing optimum activation of the phase conductors. It is then no longer possible to attain optimum torque, and the efficiency of the motor is detrimentally affected.
SUMMARY OF THE INVENTION
The object of the invention is to ensure that the motor will always be at optimum torque.
This object is attained by way of the invention recited in the major claim. Further embodiments that attain the invention will be evident from the subsidiary claims.
The invention will now be described with reference to a head-drum motor for a videorecorder.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a circuit for electronic commutation,
FIGS. 2, 3, and 4 are graphs that explicate FIG. 1, and
FIG. 5 illustrates various means of attaining the object of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The invention is illustrated in FIG. 1 by way of a circuit for commutating the head-drum motor in a videorecorder. The motor in the illustrated example has a stator with three phase belts L.sub.AB, L.sub.BC, and L.sub.CA, which drive a rotor in that the currents that flow into the belts act on permanent magnets mounted on the rotor. Rotor R is provided with markers M that commutate the motor in that they are associated with a sensor S that detects them and derives commutating pulses K from them. Indices M may consist of small magnets that operate in conjunction with a sensor in the form of a Hall generator. Indices M can also be light-permeable or reflecting points that operate in conjunction with an optical scanner or light barrier. The markers can also be magnets that operate in conjunction with a magnetic resistor. Commutating pulses K arrive at the input terminal of a counter Z that re-zeroes itself subsequent to a number of incoming pulses. This occurs in conjunction with a logic circuit L that creates a re-zeroing pulse from a desired terminal position on the part of the counter. The number x of counter pulses needed to re-zero counter Z equals a whole-number divisor of the number N of markers M on rotor R. The illustrated example utilizes 24 markers M to commutate the motor. Counter Z can for example be a synchronized BCD counter such as the Texas Instruments SN 74192. For x=6, counter Z will re-zero subsequent to 6 incoming pulses, on the occurrence of the seventh pulse, that is. The outputs from counter Z arrive in a decoder circuit D (e.g Texas Instruments 74/54) that supplies a pulse in cyclical sequence to each of its output terminals 1 through 6 whenever a commutating pulse K arrives at the input terminal of counter Z. The output terminals 1 through 6 of decoder circuit D are associa
REFERENCES:
patent: 4223261 (1980-09-01), White
patent: 4320330 (1982-03-01), Bahr et al.
patent: 4507590 (1985-03-01), Miyazaki
patent: 4511797 (1985-04-01), Pohlig et al.
patent: 4525657 (1985-06-01), Nakase et al.
patent: 4551715 (1985-11-01), Durbin
Deutsche-Thomson Brandt GmbH
Fogiel Max
Ro Bentsu
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