Circuitry for compensating for transistor parameter mismatches i

Details Circuitry for compensating for transistor parameter mismatches i Circuitry for compensating for transistor parameter mismatches i

1991-04-11

1992-03-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307512, 328166, G06G 712, H03L 700

Patent

active

050971565

ABSTRACT:
The present invention provides a circuit for eliminating quadratic and offset errors in the output of a CMOS four-quadrant analog multiplier. These errors are eliminated by feedback circuits that each include one or more CMOS four-quadrant analog multipliers.

REFERENCES:
patent: 3668440 (1972-06-01), Davis et al.
patent: 3805092 (1974-04-01), Henson
patent: 4144581 (1979-03-01), Prudente
patent: 4375013 (1983-02-01), Cointot et al.
patent: 4572975 (1986-02-01), Bowers
patent: 4906873 (1990-03-01), Shoemaker et al.
patent: 4978873 (1990-12-01), Shoemaker
Highleyman et al., "An Analog Multiplier Using Two FETs", IRE Transactions n Comm. Systems, pp. 311-317, Sep., 1962.

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