Circuitry, architecture and method (s) for phase matching...

Details Circuitry, architecture and method (s) for phase matching... Circuitry, architecture and method (s) for phase matching...

2001-09-28

2002-04-23

Mis, David (Department: 2817)

Oscillators

Ring oscillators

C331S17700V, C331S034000

Reexamination Certificate

active

06377128

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to voltage controlled oscillators (VCOs) generally and, more particularly, to circuitry, architecture and method(s) for phase matching and/or reducing load capacitance, current and/or power consumption in an oscillator.
BACKGROUND OF THE INVENTION
Voltage controlled oscillators (VCOs) are used in phase lock loops (PLLs) to generate clocks having particular frequencies. PLLs are generally considered clock multipliers. For example, an input reference clock having a frequency of 10 Mhz can be multiplied by the PLL to yield an output clock signal having a frequency of 200 Mhz. Ideally, this clock multiplication would result in an output clock that is in perfect phase/frequency with the reference clock. In clock recovery systems, the PLL is used to align a particular data pattern with the output clock. In these applications, a phase frequency detector (PFD) is used to generate the proper frequency, while a phase detector (PD) is used to align the data pattern to the output clock.
FIG. 1
illustrates a conventional phase lock loop circuit
10
. The circuit
10
has a phase detector (PD)
12
, a phase frequency detector (PFD)
14
, a loop filter
16
, a voltage control filter
18
, a voltage controlled oscillator
20
and a divider
22
. The VCO
20
presents a signal to the divider
22
. The divider
22
presents a feedback signal to the PFD
14
and the PD
12
. The PFD
14
also receives a reference clock signal. The PD
12
also receives a data signal. The difference in frequency between the reference clock and the feedback signal is used to generate two control signals that are presented to the loop filter
16
. The loop filter
16
presents a signal to the voltage controlled oscillator
20
in response to the control signals. During normal operating conditions, the reference clock is generally synchronized with the feedback signal. Such a synchronization is shown by the block
24
.
A common type of VCO that may be used in a PLL is a ring VCO.
FIG. 2
illustrates the construction of a ring VCO
30
. The ring VCO
30
comprises several inverting stages
32
a
-
32
n.
The inverting stages
32
a
-
32
n
are connected in series. An output
34
of the last stage
32
n
is looped back to an input
36
of the first stage
32
a
with enough propagation delay to allow sufficient phase margin for an inversion. The output of each stage is shifted in phase from the previous stage. The magnitude of the shift is determined by the stage delay.
A ring VCO having outputs of individual stages accessible is generally considered a multi-phase VCO. The multi-phase VCO is attractive because it allows the use of “slower” parallel architecture. A serial high speed architecture is less desirable due to the high current and timing limitations that are required. Applications of multi-phase VCOs are illustrated in
FIGS. 3A-C
.
The matching of the phase shifts of each stage is critical for many phase sensitive applications. In an application is where an XOR gate is used to multiply a clock frequency (e.g., FIG.
3
B), if the phases are not matched well, a 50% duty cycle output may not be possible. In a phase detector (PD) application (e.g., FIGS.
3
A and
3
C), a phase mismatch will result in static phase error, and/or jitter.
In order to reduce phase mismatch, the conventional approaches compensate for differences in stage delay. The compensation has included additional components or variation in the placement of the stages.
FIG. 4
is a diagram illustrating a conventional method where compensation for phase mismatch is accomplished by matched resistors and matched capacitive loading by the addition of line capacitance to compensate for load mismatch. This method only compensates for a linear silicon gradient. Interconnect lines are not matched and critical matching elements are not localized.
FIG. 5
is a diagram illustrating placement of stages to equalize interconnect line capacitance. This method matches the interconnect lines. No compensation for silicon gradient is provided. Additionally, critical matching components are not localized.
FIG. 6
is a diagram illustrating variation in the placement of the stages to compensate for the layout gradient. Variation in stage placement only compensates for a linear silicon gradient. The interconnect lines are not matched. The critical matching elements are not localized.
FIG. 7
is a diagram illustrating centroiding the stages to reduce phase mismatch. This method requires separate power buses and power supply voltage drop matching across rows. The critical nodes (control nodes) are spread across switching nodes. The critical matching elements are not localized.
FIG. 8
is a diagram illustrating the use of a 2× VCO and a divider to get a 50% duty cycle clock signal without correcting for phase mismatch. A VCO running at 2× requires high power.
The conventional methods compensate only for a linear silicon gradient or match interconnect lines. The critical matching elements remain distributed among the stages. The distributed loads must be larger to phase match the stages.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of clock signals each in response to (i) one or more control inputs and (ii) one or more of a plurality of phase timing elements. The second circuit may be configured to generate the plurality of phase timing elements.
The objects, features and advantages of the present invention include providing an apparatus that may: (i) improve the process gradient and the effect of temperature variation across a chip; (ii) provide good stage-to-stage gradient cancellation; (iii) improve resistor gradient cancellation by localizing the resistor gradient cancellation; (iv) improve resistor matching due to non-linear factors (e.g., non-linear gradient variables) while reducing load size by localizing the resistors; (v) facilitate randomizing the resistors while maintaining identical resistor gradient cancellation; (vi) reduce the layout size of the inverter stages; (vii) provide tighter layout and better matching by using space that would otherwise be wasted; and/or (viii) reduce load capacitance in each VCO stage.


REFERENCES:
patent: 3424870 (1969-01-01), Breeden et al.
patent: 3699477 (1972-10-01), McKell
patent: 4397211 (1983-08-01), Ferdinand
patent: 5302920 (1994-04-01), Bitting
patent: 5790479 (1998-08-01), Conn
FP 15.1: A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis, By Alan Fiedler et al., ISSCC97/Session 15/Serial Data Communications/Paper FP 15.3, pp. 186-187.
FP 15.3: A 1.25 Gb/s, 460 mW CMOS Transceiver for Serial Data Communication, By Dao-long Chen et al., ISSCC97/Session 15/Serial Data Communications/Paper FP15.3, pp. 190-191.

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