Circuitry and methods for high speed data encoding

Details Circuitry and methods for high speed data encoding Circuitry and methods for high speed data encoding

2007-01-02

2007-01-02

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Substituting specified bit combinations for other prescribed...

C714S752000

Reexamination Certificate

active

11221071

ABSTRACT:
An unpartitioned high-speed 8B/10B encoder and corresponding methods use only one edge or level of the clock signal per clock cycle to encode a set of 8B to a corresponding set of 10B data, and thus is not limited to a 50% clock duty cycle. The encoder includes an unpartitioned encoding circuit that receives 8B data and a special character signal and generates 10B intermediate data, a disparity control that receives the 8B data and the special character sign in parallel with that information being received by the encoding circuit, and also receives a clock signal, and generates two control signals; and logic circuitry that receives the intermediate output data and the two control signals and generates the 10B output data. The encoder may be embodied in a high-speed encoding system in which the processing speed of the encoder is greater than 250 MHz.

REFERENCES:
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 4499454 (1985-02-01), Shimada
patent: 4626826 (1986-12-01), Fukuda et al.
patent: 4855742 (1989-08-01), Verboom
patent: 5025256 (1991-06-01), Stevens
patent: 5245339 (1993-09-01), Cideciyan
patent: 5539191 (1996-07-01), Ackley
patent: 5699062 (1997-12-01), Widmer
patent: 5748119 (1998-05-01), Ko
patent: 6192027 (2001-02-01), El-Batal
patent: 6295010 (2001-09-01), Thiesfeld
patent: 6323789 (2001-11-01), Lawrence
patent: 6333704 (2001-12-01), Jung et al.
patent: 6501396 (2002-12-01), Kryzak et al.
patent: 6614369 (2003-09-01), Widmer
patent: 6617984 (2003-09-01), Kryzak et al.
patent: 6642862 (2003-11-01), Boudry
patent: 6691275 (2004-02-01), Jaeckel
patent: 6700510 (2004-03-01), Kryzak et al.
patent: 6886126 (2005-04-01), Grivna et al.
patent: 6914545 (2005-07-01), Zaidi
“A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code”, A.X. Widmer, et al., IBM J. Res. Develop., vol. 27, No. 5, Sep. 1983.

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