Circuitry and method for testing a write state machine

Details Circuitry and method for testing a write state machine Circuitry and method for testing a write state machine

1991-12-16

1994-11-29

Atkinson, Charles E.

Excavating

365201, 371 211, G01R 3128

Patent

active

053696476

ABSTRACT:
A method is described for verifying the operation of next state logic within a write state machine for automatically programming and erasing a flash memory. Verification of the next state logic's operation begins by configuring the write state machine in a test mode. Afterward, the next state logic is cycled through its possible output states by providing the next state logic with all possible input states. Outputs from next state logic are compared to expected outputs, thereby verifying the operation of the next state logic. Also described is circuitry for verifying the operation of next state logic within a write state machine. The circuitry includes test registers for storing test signals. In response to the test signals a first means isolates the next state logic from the write state machine. A second means provides alternative inputs to the next state logic in response to the test signals. Also described is circuitry and methods of testing other circuits within the write state machine, such as, the address counter, period counter, data latch comparator, etc.

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