Circuitry and method for selecting a drain programming voltage f

Details Circuitry and method for selecting a drain programming voltage f Circuitry and method for selecting a drain programming voltage f

1993-09-10

1995-03-28

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 36518909, G11C 700

Patent

active

054023700

ABSTRACT:
A nonvolatile memory residing on a single substrate is described. The nonvolatile memory includes a memory array having at least a memory cell. The memory cell includes a drain region, a source region, a control gate, and a floating gate. A drain programming voltage generation circuit is coupled to a programming voltage source and the drain region of the memory cell for providing a drain programming voltage to the drain region of the memory cell during programming of the memory cell. A control circuit is coupled to the drain programming voltage generation circuit for causing the drain programming voltage to vary with respect to a programming ability of the memory cell such that the memory cell is programmed to be within a predetermined range of a predetermined threshold voltage with a predetermined gate programming voltage for a predetermined programming time. A method for setting the drain programming voltage for the nonvolatile memory such that the drain programming voltage varies inversely with respect to the programming ability of the nonvolatile memory is also described.

REFERENCES:
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5218571 (1993-06-01), Norris
patent: 5253201 (1993-10-01), Atsumi et al.
patent: 5293344 (1994-03-01), Akaogi

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