Circuitry and method for reset discrimination

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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327 34, 327160, 327198, H03K 1722

Patent

active

054423104

ABSTRACT:
A reset discrimination circuit for identifying the completion of power-up via a valid deassertion of an external reset signal is described. When power-up is complete the reset discrimination circuit brings a function enable signal active, which initially powered up in the inactive state. The reset discrimination circuit includes a synchronous edge detector, a high counter, and a low counter. The synchronous edge detector detects the active state of the external reset signal and generates a first reset signal, which resets the high counter. After counting M clock pulses during the active state of the external reset signal the first counter enables the low counter. The low counter counts N clock pulses during the inactive state of the external reset signal to identify its valid deassertion. A method of identifying the completion of power-up by identifying the valid deassertion of an external reset signal is also described.

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