Boots – shoes – and leggings
Patent
1993-03-25
1997-01-28
Treat, William M.
Boots, shoes, and leggings
395800, 364DIG2, G06F 930
Patent
active
055985459
ABSTRACT:
Circuitry and method for performing a double instruction during a single clock cycle in a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The circuitry includes four sense amps per processor element and one ALU to enable reading of four data bits per clock cycle. The method includes reading data from each register file in a processor element and writing the data in one of the register file memory banks; enabling a 2:1 reduction in the amount of required instructions and a substantial reduction in overall cycle time.
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Childers Jim
Reinecke Peter
Takahashi Yutaka
Yamamoto Seiichi
Donaldson Richard L.
Kesterson James C.
Marshall, Jr. Robert D.
Texas Instruments Incorporated
Treat William M.
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