Circuitry and method for latching information

Details Circuitry and method for latching information Circuitry and method for latching information

1996-05-28

1999-12-14

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327218, 327212, H03K 3356

Patent

active

06002285&

ABSTRACT:
An output signal is output to a selected one of first and second output nodes in response to an event in which a control node transitions from a first logic state to a second logic state. The selected one of the first and second output nodes is selected in response to a logic state of an input node during the event. A minimum setup time for the logic state of the input node to be stable before the control node transitions to the second logic state is shorter than a minimum time for inverting the logic state of the input node.

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patent: 5497115 (1996-03-01), Millar et al.
patent: 5517542 (1996-05-01), Huq
IBM Technical Disclosure Bulletin, "Delta-I Simultaneous Switching", vol. 27, No. 4A, Sep. 1984, pp. 2048-2053.

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