Circuitry and a method for introducing a delay

Details Circuitry and a method for introducing a delay Circuitry and a method for introducing a delay

1999-12-17

2001-11-20

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S277000

Reexamination Certificate

active

06320445

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to circuitry for introducing a delay and a method for introducing a delay and in particular, but not exclusively to a method and circuitry for introducing a delay to an output clock signal.
BACKGROUND OF THE INVENTION
Clock signals are used to control the timing of circuits and for example control when signals are to be applied and when certain operations are to commence. one example of a known arrangement which uses clock signals is shown in
FIG. 1. A
synchronous dynamic random access memory SDRAM
2
receives three inputs
4
,
6
and
8
from an interface
10
. The first input
4
provides a clock signal, the second input
6
provides data to be written into the SDRAM
2
whilst the third input
8
provides the address at which the data is to be written. The clock signal input to the SDRAM
2
from the first input
4
controls the timing of the operation of the SDRAM
2
such as the opening and closing of pages of the SDRAM
2
and the writing of the data into the required locations.
The clock signal input to the SDRAM
2
is generated from the internal clock &phgr; of the interface
10
. The internal clock &phgr; passes through elements which introduce varying amounts of delay. These elements are represented by delay
14
. In practice the amount of delay provided by the delay elements varies over time, for example due to changes in temperature. The interface
10
uses the internal clock &phgr; to control the timing of the data and address signals. In order to ensure that the SDRAM
2
operates correctly, it should be ensured that the internal clock &phgr; signal is in phase with the clock signal output by the interface
10
. Generally, problems are avoided if the internal clock &phgr; is in phase with the output clock even if the output clock is delayed with respect to the internal clock &phgr;. A number of solutions have been proposed to ensure that the internal clock &phgr; and the output clock are in phase.
In one solution, the internal clock &phgr; is input to a variable delay
12
, the output of which is connected to delay
14
which varies with time due to changes in temperature. The output of the delay
14
provides the clock output of the interface
10
which is input to the SDRAM
2
. The internal clock &phgr; is also input to a comparator
16
which also receives the output from the delay
14
. The comparator
16
compares the phase of the internal clock &phgr; with the phase of the signal output by the delay
14
. The comparator
16
generates a control signal which is output to the variable delay
12
based on the results of the comparison. The control signal is arranged to cause the delay provided by the variable delay
12
to be such that the phase difference between the compared signals is n×360° where n is an integer.
The variable delay
12
can take the form shown in FIG.
2
. The variable delay
12
shown in
FIG. 2
provides a single delay path with a series of outputs
20
along its length. Each of the outputs
20
provide a different delay with those outputs
20
which are closest to the input providing the shortest delays and those outputs closest to the output of the variable delay
12
providing the longest delays. The delay provided by the variable delay
12
is varied by selecting the appropriate output. Consider the case where the delay provided by variable delay
12
is being reduced and the output nearest to the input of the variable delay provides the current output with a delay of x°. In order to effectively reduce the phase by y° it is necessary to go to the output which provides a delay of 360+(x−y)°. In order to ensure that this transition is available, it is necessary to ensure that the delay values of x and (x−y)+360° are both available at the same time and that the delay can be adjusted as required. These two requirements results in the need for two control loops one for defining the active part of the path and one loop to select the required delay from the active path. The active part of the delay path is that part of the path from which the delay outputs are taken. Transitions can thus be made from one part of the path to another as described hereinbefore. Typically, the path is regulated to ensure that its length is one clock cycle and that the required delay is selected from an appropriate point along it.
The provision of a multi output variable delay is disadvantageous in that the delay itself as well as the regulation mechanism can be costly in terms of silicon area. Additionally the regulation mechanism is an analogue structure which can be complex to design.
As an alternative to the regulation of the path, the variable delay can be constructed to be much longer than one clock cycle so that sufficient delay and resolution are always available. However, this solution also requires a large silicon area.
Variable delay paths with single outputs are known but also suffer from the problems relating to transitions from a delay of a° to a delay of a+360°.
Another solution which has been proposed to deal with the alteration in the phase of the clock signal output by the interface
10
as compared to the internal clock signal &phgr; is to use a phase locked loop. However, this solution is disadvantageous in that phase locked loops are not particularly robust and are complex. Accordingly it is preferred to avoid the use of phase locked loops in at least some applications.
SUMMARY OF THE INVENTION
It is therefore an aim of some embodiments of the present invention to overcome or at least mitigate the problems described hereinbefore.
According to one aspect of the present invention, there is provided circuitry for introducing a delay to a signal comprising input means for receiving the signal to be delayed; a first delay path; a second delay path; and selection means for causing the signal passing through a selected one of the delay paths to be output from said circuitry.
By having two separate delay paths, it is possible to switch between the paths. This makes it simpler, as compared to the arrangements described hereinbefore, to control the delay, particularly when the ends of the delay paths are reached. In embodiments of the present invention, the two delay paths may be shorter than those of the prior art and additionally simpler.
Preferably, at least one of said first and second paths are variable delay paths. One path may be fixed in length. One path, preferably a fixed length path may be shorter than the other path. It is also preferred that the variable delay paths only provide a single output.
Preferably, delaying means are arranged between an output of the selected delay path and the output of the circuitry. The delaying means may take the form of any suitable elements which may introduce a delay, such as a driver or the like.
Comparing means are preferably provided for comparing the phase of the signal output by said circuitry and the phase of the signal prior to being input to the selected path. In this way, it can be determined whether or not the correct delay is being provided by the selected path and if not the delay provided by the selected delay path can be altered. Accordingly, the output of the comparing means preferably provides an output signal which is used to determine the delay provided by the selected delay path. The output signal may be arranged to determine the delay provided in a selected delay path so that the phase difference between the signal output by the circuitry and the signal input to the selected delay path is substantially equal to n×360°, where n is an integer.
Preferably, the delay introduced by the selected delay path is less than or equal to 1 cycle.
The signal to be delayed is preferably input to both the first and second delay paths. Comparator means are preferably provided for comparing the phase of the signals output from the first and second delay paths. The output of the comparator means may be used in controlling the switching between the selected and deselected path.
Preferably, control means are a

Affiliated with

Also associated with

Rating

Circuitry and a method for introducing a delay does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuitry and a method for introducing a delay, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuitry and a method for introducing a delay will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2577421