Circuitized semiconductor structure and method for producing...

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Reexamination Certificate

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C428S620000, C428S621000, C428S675000, C428S668000, C428S209000, C428S220000, C428S457000, C428S596000, C438S677000, C438S678000, C438S674000, C438S687000, C438S964000, C430S315000, C430S319000

Reexamination Certificate

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06265075

ABSTRACT:

TECHNICAL FIELD
The present invention relates to circuitized semiconductor structures and especially to structures having enhanced copper adhesion. The present invention makes it possible to provide fine line circuitized substrate structures. The present invention also provides a method for fabricating the circuitized semiconductor structure.
BACKGROUND OF INVENTION
In the manufacture of circuitized semiconductor carrier structures, a dielectric sheet material is employed as the substrate. A conductive circuit pattern is provided on one or both of the major surfaces of the substrate.
A conductive pattern can be formed on the surface of the substrate using a variety of known techniques. These known techniques include the subtractive technique, where a layer of copper is etched to form the desired circuit pattern, the EDR (electroless direct bond) technique, where copper is electrolessly plated directly on the surface of the substrate in the desired pattern, and the peel-apart technique, where the desired circuit pattern is plated up from a thin layer of peel-apart copper.
If it is desired to use the EDB technique, it is necessary to plate directly on the surface of the substrate.
Since the dielectric substrate is nonconductive, in order to plate on the substrate, the substrate must be seeded or catalyzed prior to the deposition of metal onto the substrate.
The electroless plating of copper onto a substrate is well-known in the art. For instance, an electroless or autocatalytic copper plating bath usually contains a cupric salt, a reducing agent for the cupric salt, a chelating or complexing agent, and a pH adjustor. In addition, if the surface being plated is not already catalytic for the deposition of the desired metal, a suitable catalyst is deposited onto the surface prior to contact with the plating bath. Among the more widely employed procedures for catalyzing a surface is the use of stannous chloride sensitizing solution and a palladium chloride activator to form a layer of metallic palladium particles.
Although the technology relative to electroless copper plating is continually being improved, there still remains room for additional improvement. Certain problems are specially pronounced when preparing structures having very fine line (down to 0.5 mil lines and 0.5 mil spaces) circuitization. The fine features typically have only been created for very short distances and only when needed for escaping a tight grid (down to 0.5 mm) pitch. Several problems currently exist that prohibit using thin film circuitization for global wiring on, for instance, rigid PWB (printed wire board).
The main problems are adhesion of the copper circuit to the laminate over long lengths (one inch or greater), insulation resistance between circuits as lines per channel increase, cross-sectional area of the circuits are limited with current techniques so that resistance losses prevent global wiring and use of current techniques is limited for build-up layers.
SUMMARY OF INVENTION
The present invention provides structures exhibiting high copper circuitry to substrate adhesion. Moreover, the present invention provides for excellent insulation resistance protection. The present invention also makes it possible to achieve long circuit lengths at a high density for global wiring. The present invention permits global wiring for a very dense and high I/O package.
More specifically, the present invention provides a circuitized semiconductor structure which comprises:
a layer of dielectric material;
a catalyst seed layer located on the layer of dielectric material;
a layer of photoimageable dielectric material on the catalyst seed layer and having openings therein for exposing portions of the catalyst seed layer;
a layer of nickel deposited in the openings of the layer of photoimageable dielectric material and on top of the catalyst seed layer; and
a layer of copper plating in the openings and over the layer of nickel and being coplanar with the top of the layer of photoimageable dielectric material.
The present invention also relates to fabricating the above disclosed circuitized semiconductor structure. The method comprises:
providing a layer of dielectric material;
depositing a catalyst seed layer on the layer of dielectric material;
depositing a layer of photoimageable dielectric material on the catalyst seed layer;
imagewise exposing the layer of photoimageable dielectric material and developing to provide openings in the layer of photoimageable dielectric material to expose portions of the catalyst seed layer;
depositing a layer of nickel in the openings of the layer of photoimageable dielectric material and on top of the catalyst seed layer; and
depositing a layer of copper plating in the openings and over the layer of nickel, and wherein the layer of copper plating is coplanar with the top layer of the layer of photoimageable dielectric material.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.


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Research Disclosure No. 324026, Apr. 10, 1991.

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