Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
2000-07-07
2001-10-23
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S437000, C365S218000
Reexamination Certificate
active
06307420
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a circuit for overcoming voltage loss in an NMOS transistor, and more particularly to using a controlled PMOS transistor to overcome the voltage loss in an NMOS transistor.
BACKGROUND OF THE INVENTION
NMOS transistors are widely used in integrated circuit applications. One application is in a programmable logic device (PLD), such as a field programmable gate array where voltage passes through an NMOS transistor to erase a flash memory cell. Flash memory cells are erased by gradually applying an erasing voltage to an erase pin on the memory cell.
A drawback to using an NMOS transistor to supply an erasing voltage to a memory cell is that an NMOS transistor does not provide the full input voltage to the memory cell and thus does not “efficiently” erase the memory cell. As is known in the art, the efficiency of a memory cell erasure is defined in terms of a subsequent voltage on the gate of the memory cell required to read the cell. The more efficiently a memory cell is erased, the lower a voltage required to read the memory cell. The less efficiently a memory cell is erased, the higher a voltage required to read the memory cell. The NMOS transistor does not provide the full input voltage to the memory cell partly because of a “body effect”, voltage loss that it experiences. The body effect voltage loss of NMOS transistors is discussed in “Principles of CMOS VLSI Design,” by Weste and Eshraghian©1985, pp. 38-39.
As an example, if a flash memory cell requires 12V at its erase pin for the memory cell to be efficiently erased, then an NMOS transistor receiving an erasing voltage of 12V would be inadequate, since typically the total threshold voltage loss of the NMOS transistor would limit the voltage seen at the erase pin of the memory cell to only 10.5V.
There have been two main approaches for overcoming the voltage loss of NMOS transistors. A first approach has been to increase the erasing voltage applied to the input of the NMOS transistor. Increasing the erasing voltage, however, increases the chances of dielectric breakdown within the NMOS integrated circuit. While integrated circuit manufacturers could enhance their fabrication processes to reduce the possibility of dielectric breakdown, to do so would increase the price of an integrated circuit.
A second approach has been to replace the NMOS transistor with a PMOS transistor. A PMOS transistor typically does not suffer voltage loss at higher voltages since its source and body are electrically coupled. However, a PMOS transistor unfortunately does not lend itself to controlled and gradual ramping of its output voltage in response to a gradual ramping of its gate voltage. In fact, a PMOS transistor is almost totally off until its gate voltage reaches its threshold voltage, and thereafter is fully on.
What is needed is a circuit that overcomes the voltage loss in an NMOS transistor and which addresses the limitations of the prior art described above.
SUMMARY OF THE INVENTION
The present invention is a circuit that overcomes a voltage loss of an NMOS transistor. Within the circuit of the present invention, a first NMOS transistor receives an input voltage and passes a gradually increasing output voltage in response to a ramping voltage which is applied to the gate of the NMOS transistor. A first PMOS transistor, which also receives the input voltage, is gated by a control circuit. The control circuit receives the ramping voltage, and when the ramping voltage reaches a predetermined voltage level, the control circuit switches on the PMOS transistor. The PMOS transistor then passes the input voltage as the output voltage. Thus, the output voltage passed by the NMOS transistor increases in response to the ramping voltage, and because of the threshold voltage drop of the NMOS transistor, the output voltage passed by the NMOS transistor is less than the input voltage. However, when the PMOS transistor is switched on, the full input voltage is passed by the PMOS transistor as the output voltage.
In another aspect of the invention, the control circuit includes a second PMOS transistor, a clamping circuit, and a second NMOS transistor. The output of the second PMOS transistor gates the first PMOS transistor, the second PMOS transistor being gated by the ramping voltage and receiving the input voltage.
The output of the clamping circuit in combination with the second NMOS transistor also gate the second PMOS transistor. The clamping circuit supplies a voltage that will switch on the second PMOS transistor. The output voltage of the clamping circuit is supplied as the input voltage to the second NMOS transistor, which is gated by the ramping voltage. Thus, when the second PMOS transistor is switched off, the second NMOS transistor is switched on and the voltage from the clamping circuit is supplied to switch on the first PMOS transistor. When the first PMOS transistor is switched on, the full input voltage is supplied as the output voltage.
In still another aspect of the invention, the circuit that overcomes the threshold voltage drop voltage loss of an NMOS transistor is used to supply an erasing voltage to a memory cell. Certain memory cells require a gradual increase in an erasing voltage level, and in addition, require a threshold erasing voltage level. The above described circuit is suitable for erasing such a memory cell because it supplies a gradually increasing output voltage via the first NMOS transistor. When the first PMOS transistor is switched on, the full input voltage is passed as the output voltage to erase the memory cell.
The circuit of the present invention is particularly advantageous over the prior art because the erasing voltage provided to the memory cell is not limited by the threshold voltage drop of the NMOS transistor within the circuit.
These and other aspects of the invention will be recognized by those skilled in the art upon review of the detailed description, drawings, and claims set forth below.
REFERENCES:
patent: 4001606 (1977-01-01), Dingwall
patent: 4611135 (1986-09-01), Nakayama et al.
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4825101 (1989-04-01), Walters, Jr.
patent: 5182479 (1993-01-01), Behagel et al.
patent: 5563540 (1996-10-01), Ashley et al.
patent: 6072353 (2000-01-01), Matsuzawa
Neil H. E. Weste and Kamran Eshraghian, “Principles of CMOS VLSI Design, A Systems Perspective”, Addison Wesley Publishing Company, reprinted Jun. 1988, Copyright 1985 by AT&T Bell Laboratories and Kamran Eshraghian, pp. 38-39.
Cunningham Terry D.
Xilinx , Inc.
Young Edel M.
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