Circuit with ramp-up control and overcoming a threshold voltage

Details Circuit with ramp-up control and overcoming a threshold voltage Circuit with ramp-up control and overcoming a threshold voltage

1997-01-10

2000-08-01

Cunningham, Terry D.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

327437, 365218, H03K 1716

Patent

active

060972386

ABSTRACT:
A ramping circuit gradually applies an erasing voltage to a memory cell. Within the ramping circuit an NMOS transistor is disclosed which gradually supplies the erasing voltage to the memory cell in response to an external ramping voltage. The NMOS transistor supplies the erasing voltage until the body effect loss voltage of the transistor limits a maximum erasing voltage that the NMOS transistor can supply. The specification then discloses a PMOS transistor which operates to supply the erasing voltage to the memory cell when the NMOS transistor can no longer do so. The PMOS transistor is connected to control circuitry which keeps the PMOS transistor inactive until the output voltage of the NMOS transistor is limited by its body effect voltage loss.

REFERENCES:
patent: 4001606 (1977-01-01), Dingwall
patent: 4611135 (1986-09-01), Nakayama et al.
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4825101 (1989-04-01), Walters, Jr.
patent: 5182479 (1993-01-01), Behagel et al.
patent: 5563540 (1996-10-01), Ashley et al.
Neil H. E. Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design, A Systems Perspective", Addison Wesley Publishing Company, reprinted Jun. 1988, Copyright 1985 by AT&T Bell Laboratories and Kamran Eshraghian, pp 38-39.

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