Circuit with predetermined delay for selectively relaying interr

Details Circuit with predetermined delay for selectively relaying interr Circuit with predetermined delay for selectively relaying interr

1990-01-30

1994-03-08

Lee, Thomas C.

Boots, shoes, and leggings

3642293, 3642302, 3642294, 364DIG1, 364268, 3642689, 371 112, 371 111, G06F 1337

Patent

active

052935892

ABSTRACT:
A computer having a plurality of plug-in modules is provided with a holding circuit for transmitting an interrupt signal over an interrupt signal line. The holding circuit conducts the interrupt signal in the appropriate manner regardless of whether or not a given module is plugged in. At the same time it ensures that a plugged-in module responds to the interrupt signal in the appropriate manner.

REFERENCES:
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patent: 4604689 (1986-08-01), Burger
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patent: 4633392 (1986-12-01), Vincent et al.
patent: 4799148 (1989-01-01), Nishioka
patent: 4914625 (1990-04-01), Billian
patent: 5083259 (1992-01-01), Maresh et al.
patent: 5117494 (1992-05-01), Costes et al.
The VMEbus Handbook, published by VMEbus Internatinal Trade Association of Scottsdale, Ariz., pp. 78-83 (1989).
R. E. Russell et al.: "Interrupt request circuit" in: IBM Technical Disclosure Bulletin, vol. 27, No. 1B, Jun. 1984; pp. 554-556.

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