Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-09-07
2001-08-14
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185030, C365S218000
Reexamination Certificate
active
06275418
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of erasing a non-volatile memory a number of bits at a time and to an integrated circuit that comprises a non-volatile memory.
U.S. patent application Ser. No. 5,844,842 discloses a Flash EEPROM device. The memory contains a matrix of memory transistors, organized in columns of transistors that have their main current channel connected in common to a bit-line for the column. Transistors in the same row have their control terminals connected together. In a flash memory information is stored by adjusting the threshold of memory transistors.
A typical memory transistor is a field effect transistor with a floating gate, whose threshold can be adjusted by injecting or removing charge carriers from the floating gate. Initially, the threshold of all memory transistors is at a first level, the erased level, which represents a first logical value. If a different logical value has to be stored at some locations in the memory, the threshold of the transistors that correspond to the relevant memory locations must be shifted. The memory shifts these thresholds to a second level, the programmed level. This is called programming.
In a read operation a transistor is selected from a column and the threshold of the selected transistor is sensed. For this purpose the memory supplies the selected transistor with a gate-source voltage between the programmed and erased level. As a result, the main current channel of the selected transistor will or will not conduct current, depending on whether the threshold of the transistor has or has not been programmed. The other transistors that are connected to the same column are prevented from delivering current to the bit-line. As a result, the logical value stored in the selected transistor can be determined from the current through the bit-line .
After the memory has been programmed with information the memory must be erased before different logical information can be stored. In a flash memory a block of memory transistors, for example a sector consisting of a number of rows of the matrix, is erased as a whole.
As described in the prior art, it is important that the threshold of all memory transistors is shifted back sufficiently to the erased level. To ensure this, the memory performs erasing in repeated steps. In each step threshold shifting signals are applied to all transistors in the sector. After each step the memory reads information successively from the different memory transistors in the sector. The erase steps are repeated until the read-out logic information level in all transistors corresponds to the erased level.
SUMMARY OF THE INVENTION
It is an object of the invention to reduce the time needed for erasing information from the memory.
Claim
1
describes a method of erasing information according to the invention. According to the invention a number of transistors in the same column (preferably all transistors that are part of an erased sector) are read out collectively to determine whether they have been erased properly. This contrasts with the prior art where the transistors in the same column are read out one by one. The determination is performed by selecting more than one transistor in the column at the same time. The resulting collective current through the bitline from all the selected transistors is used to determine a logical read-out value of the memory, which signals whether the current is in a predetermined range or not (preferably the current range corresponding to one of the possible logical states of a single storage transistor in normal use). Dependent on the logical read-out value erasing is repeated or not.
Preferably, the bitlines of several columns are conductively connected to each other. The resulting combined collective current from the se several bitlines is then used to determine the logical read-out value. This is particularly useful in a memory in which normal read-out of programmed data involves connection of a sense amplifier to a selectable one of the bit-lines for a number of columns. In such a memory only one sense amplifier is provided for a number of columns. By connecting the bit-lines for those columns to the sense amplifier collectively, proper erasure of a number of columns can be tested simultaneously with the available sense amplifier.
Preferably, all transistors in a column or a number of columns of the erased sector are selected together to test whether they have been properly erased. In this way the test of an entire sector can be performed in one read operation.
The idea behind the invention is that the collective current provides sufficient information to decide whether an additional erase step is to be performed in any one of the selected transistors. For the purpose of deciding about an erase step it is not necessary to examine currents from individual transistors separately.
In one embodiment, where the threshold voltage is raised during erasing, none of the selected transistors will eventually draw any significant current once the transistors have been sufficiently erased. In case of sufficient erasure, the collective current through a plurality of selected transistors is therefore much less than the current through a single transistor that has not been erased.
If any one of the transistors is insufficiently erased, more current will flow through the bitline. This current can be distinguished from the insignificant current that flows through the bitline after sufficient erasure, preferably using the sensing circuit that is normally used for distinguishing the erased and programmed state of individual transistors. If too much current flows, an additional erase step must be performed.
If more than one of the transistors is insufficiently erased, more current will be drawn, but this should lead to the same response: performing an additional erase step. So for the purpose of deciding about an additional erase step it suffices to determine whether the collective current is larger than a predetermined value.
In another example, the threshold voltage is lowered during erasing. In this case, the transistors will draw current once they are sufficiently erased. Erasing is performed in steps and performance of the steps is stopped before the threshold of any of the transistors is over erased. For this purpose a lower gate source voltage is applied to the transistors collectively than during normal read out of individual transistors.
As long as none of the transistors is over erased, an insignificant current will flow, which is smaller than the current through an individual transistor in the erased state during normal readout. In this case, erasing may be repeated. When at least one of the transistors threatens to become over erased, more current will flow and no additional erase steps will be performed. In case more transistors threaten to become over erased, there is simply more current and no erase needs to be performed either. So for the purpose of deciding about an additional erase step it suffices to determine whether the collective current is smaller than a predetermined value.
REFERENCES:
patent: 5835415 (1998-11-01), Harari
patent: 5844842 (1998-12-01), Seki et al.
patent: 0572240A2 (1993-12-01), None
Biren Steven R.
Lam David
Nelms David
U.S. Philips Corporation
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