Circuit with FET transistor pair

Details Circuit with FET transistor pair Circuit with FET transistor pair

2002-06-13

2003-03-04

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Slope control of leading or trailing edge of rectangular or...

C327S427000, C327S389000

Reexamination Certificate

active

06529056

ABSTRACT:

BACKGROUND
This invention relates to transistor switches, and more particularly to metal oxide semiconductor field-effect transistor (MOSFET) switches.
In power management ICs having a monolithically integrated MOSFET power train, the on-chip field-effect transistor (FET) not only accounts for most of the power dissipation, but also consumes a significant amount of silicon area, and very often is the major concern regarding the long-term reliability of the chip.
FIG. 1
shows a cross-sectional view of a conventional asymmetric high-voltage NMOS transistor, compatible with standard CMOS processes, with N deep drain (NDD) implantation. Although implementations of the inventions are described with reference to an asymmetrical device, the invention applies to all MOSFET devices.
A N+ source
104
is formed within a P substrate
102
. Also formed in the substrate is a NDD region
106
that includes a N+ drain implant
108
, and a N lightly doped drain (LDD) implant
1
12
. Formed upon substrate
102
is a LDD that includes a gate
114
.
Two important dimensions in this device structure are the length L
G
of gate
114
and the spacing L
D
between the drain N+ implant
108
and gate
114
. The design rules for these two dimensions are set to meet two specifications punch-through breakdown voltage, and hot-carrier lifetime.
Quite often, it is the reliability specification, also referred to as the hot-carrier lifetime specification, instead of the punch-through breakdown voltage specification, that determines the design rule, which dictates the minimum allowed dimensions of L
G
and L
D
.
In other words, in the applications where hot-carrier degradation is not of concern, a more aggressive design rule can be used to design a transistor such as that shown in
FIG. 1
while still meeting the same punch-through breakdown voltage specification. A FET structure with smaller dimensions on L
G
or L
D
is preferred because it not only reduces the overall chip area, but also reduces the on resistance and the junction capacitance of the FET, thus improving the overall system efficiency.
It is known that hot-carrier injection (HCI) occurs at the overlapping period between the transitions of the gate voltage and drain voltage of the FET, with the injection peaking when the gate voltage is approximately one half of the drain voltage. As a result, the typical inverter application turns out to be a stressful operation for the FET in terms of hot-carrier degradation. HCI is discussed in greater detail in W. Weber, C. Werner and A. V. Schwerin, “Lifetimes and substrate current in static and dynamic hot-carrier degradation, ” IEDM 86, pp 390-393, 1986.
FIG. 2
is a conceptual time t versus voltage v plot of voltage waveforms for a conventional N-FET during the switching transitions of a typical inverter mode operation. During the turn-on transition, the drain voltage V
D
goes low and the gate voltage V
G
goes high. During the turn-off transition, V
P
goes high and V
G
goes low. The area between times t
1
and t
2
and t
3
and t
4
shows the transition period during which a strong hot-carrier injection occurs. Hot-carrier degradation results in threshold voltage shift and transconductance degradation for the N-FET. Due to the hot-carrier degradation concern, the conventional design of a FET switch typically involves trade-offs between electrical performance, such as on resistance, and reliability performance, such as hot-carrier lifetime. In general, making a conventional device more resilient to hot carrier degradation involves increasing one or both of L
G
and L
D
, while improving electrical performance (and minimizing device area) involves minimizing L
G
and L
D
.
SUMMARY
In general, in one aspect, the invention features a method and computer program product for use with a switch having a field-effect transistor (FET). It includes restricting the drain-source voltage of the FET to a predetermined range; and then switching the FET.
Particular implementations can include one or more of the following features. It includes delaying switching for a predetermined period of time after restricting. It includes delaying switching for a period of time after restricting that is determined by the drain-source voltage of the FET. It includes releasing the drain-source voltage of the FET after switching. The switch includes a further FET having a drain coupled to the drain of the FET and a source coupled to the source of the FET, and restricting includes controlling the further FET. Restricting includes turning on the further FET; and switching includes turning on the FET. Restricting includes keeping the further FET on; and switching includes turning off the FET. It includes keeping the FET, off when the current at the drain is below a predetermined threshold current.
In general, in one aspect, the invention features a circuit having source, drain and gate terminals. It includes a first field-effect transistor (FET) having a first drain coupled to the drain terminal and a first source coupled to the source terminal; a second FET having a second drain coupled to the drain terminal and a second source coupled to the source terminal; and a control circuit coupled to the gate terminal, the first gate, and the second gate.
Particular implementations can include one or more of the following features. The control circuit is coupled to the drain terminal. The control circuit is configured to turn on the second FET before turning on the first FET. The control circuit is configured to impose a fixed delay between turning off the first and second FETs. The control circuit is configured to impose a delay between turning on the first and second FETs, the duration of the delay determined by the voltage between the drain and source terminals. The control circuit is configured to turn off the second FET after turning off the first FET. The control circuit is configured to impose a fixed delay between turning on the first and second FETs. The first FET is designed for superior electrical performance. The second FET is designed for superior reliability performance. The first and second FETs are implemented as a single monolithic device. The first and second; FETs and the control circuit are implemented as a single monolithic device. The circuit includes a current sensing circuit configured to keep the first FET off when the current at the drain terminal is below a predetermined threshold current.
Advantages that can be seen in implementations of the invention include one or more of the following. Implementations of the invention provide cost reduction, efficiency improvement and reliability enhancement in switching applications. Because the helper FET only accounts for a small percentage of the total FET switch size, designers can cut the overall FET switch area while improving overall switching efficiency. This approach successfully overcomes the tradeoff between electrical performance and reliability performances of conventional MOSFET switches.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.


REFERENCES:
patent: 5483188 (1996-01-01), Frodsham
patent: 5701090 (1997-12-01), Hidaka et al.
patent: 5777944 (1998-07-01), Knaack et al.
patent: 5852579 (1998-12-01), Arcoleo et al.

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