Circuit with a single address register that augments a memory co

Static information storage and retrieval – Magnetic bubbles – Guide structure

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395432, 36523008, G06F 1200

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active

055663184

ABSTRACT:
A single address register control technique for a memory controller allows both cache "reads" and page-mode "writes" to be implemented without requiring separate hardware address registers for each function. Because both functions may be implemented with virtually no performance loss in a high performance memory system using a single address register, a comparator, and one additional register, the costs and other disadvantages inherent in otherwise replicating control registers are obviated.

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