Circuit which detects a signal in successive frames by feeding b

Details Circuit which detects a signal in successive frames by feeding b Circuit which detects a signal in successive frames by feeding b

1995-09-11

1998-04-14

Lee, Thomas C.

Multiplex communications

Wide area network

Packet switching

39520062, 39520066, 39520078, 39542111, 395898, 370506, 370509, 370513, G06F 15163, G06F 1300

Patent

active

057403724

ABSTRACT:
A signal detection circuit receives a data stream containing a signal to be detected and detects the contained to-be-detected signal. The signal detection circuit includes a memory circuit prestoring data for detecting the to-be-detected signal, a first data feeder for feeding data to the memory circuit per given time slot as an upper address, and a second data feeder for feeding data to the memory circuit as a lower address using data outputted from the memory circuit. The memory circuit outputs data stored in a storage area defined by the upper address and the lower address fed from the first and second data feeders, respectively. By arranging the memory circuit to output a given value as the foregoing output data when the to-be-detected signal is detected, detection of the to-be-detected signal is achieved.

REFERENCES:
patent: 4301534 (1981-11-01), Genter
patent: 4596981 (1986-06-01), Ueno et al.
patent: 4920546 (1990-04-01), Iguchi et al.
patent: 4984249 (1991-01-01), Long et al.
patent: 5113395 (1992-05-01), Murakami et al.
patent: 5335228 (1994-08-01), Bottiglieri et al.
patent: 5367543 (1994-11-01), Uomoto
patent: 5526297 (1996-06-01), Snyder, Jr. et al.

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