Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2009-03-03
2011-10-11
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S106000, C716S110000, C716S126000, C716S136000, C716S137000
Reexamination Certificate
active
08037436
ABSTRACT:
A circuit verification apparatus for verifying justice of wiring connections of PWB is provided. The circuit verification apparatus includes a net list reduction part for generating a reduction net list in which unnecessary components and connections for verification are eliminated from connection relationships for all components used in the PWB; a connection rule for defining conditions of a pair of start point and end point of each expected connection by using variables and function; a rule expanding part for developing the connection rule by using conditions of a pin specified to the start point, determining end point conditions corresponding to the start point and generating a post-development rule including developed conditions of the start point and end point; and a net list and rule matching verification part for verifying matching state of each connection with referring to the reduction net list and the post-development rule, and outputs a verification result.
REFERENCES:
patent: 7657853 (2010-02-01), Sato et al.
patent: 2003/0046644 (2003-03-01), Wheeler et al.
patent: 2007/0180422 (2007-08-01), Cromity et al.
patent: 2008/0092089 (2008-04-01), Kobayashi
patent: 2008/0244484 (2008-10-01), Kumazaki
patent: 2008/0301600 (2008-12-01), Kumagai
patent: 2009/0055784 (2009-02-01), Izumi et al.
patent: 2009/0293027 (2009-11-01), Yamazaki et al.
patent: 1991028971 (1991-02-01), None
patent: 1994120345 (1994-04-01), None
patent: 1997-167170 (1997-06-01), None
patent: 1997-237289 (1997-09-01), None
patent: 1998-254938 (1998-09-01), None
patent: 11-102379 (1999-04-01), None
patent: 2001325315 (2001-11-01), None
patent: 2004280279 (2004-10-01), None
patent: 2005196681 (2005-07-01), None
patent: 2007094506 (2007-04-01), None
patent: 2008009574 (2008-01-01), None
Japanese Office Action for JP2009-032247 issued Mar. 23, 2010.
Dinh Paul
NEC Corporation
Nguyen Nha
LandOfFree
Circuit verification apparatus, a method of circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit verification apparatus, a method of circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit verification apparatus, a method of circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4284493