Circuit verification accessory

Details Circuit verification accessory Circuit verification accessory

1989-07-25

1990-06-26

Smith, Jerry

Excavating

371 161, 371 251, 364578, G06F 1100

Patent

active

049378279

ABSTRACT:
A hardware modeling system 10 simulates portions of electrical circuits 16, 18 utilizing actual hardware components in the simulation. Access to these hardware modeling elements 16, 18 is provided on a shared basis to plural workstations 14. Simulation vectors for plural users may be stored discontiguously in a first memory 26 and a single user's vectors are transferred to a second memory 28 for streaming to the elements 16, 18. An optional timing analyzer and memory circuit 34 periodically samples outputs from pins of the hardware modeling elements to provide timing information on the response of such elements. High impedance testing and bus contention detection is performed on the pins of the hardware modeling elements. Clocking signals applied to the hardware modeling elements are adjustable and may be set at extremely high frequencies. A special gating circuit 292 accesses each pin of the hardware modeling elements and incorporates one or more of the above features.

REFERENCES:
patent: Re31056 (1982-10-01), Chau et al.
patent: 3673397 (1972-06-01), Schaefer
patent: 3715573 (1973-02-01), Vogelsberg
patent: 3739349 (1973-06-01), Burdette, Jr. et al.
patent: 3764995 (1973-10-01), Helf, Jr. et al.
patent: 3832535 (1974-08-01), De Vito
patent: 3872441 (1975-03-01), Cailow
patent: 3932843 (1976-01-01), Trelut et al.
patent: 4000460 (1976-12-01), Kadakia et al.
patent: 4213253 (1980-07-01), Gudelis et al.
patent: 4236246 (1980-11-01), Skilling
patent: 4370728 (1983-01-01), Coffron
patent: 4397021 (1985-08-01), Lloyd et al.
patent: 4402055 (1983-08-01), Lloyd et al.
patent: 4451918 (1984-05-01), Gillette
patent: 4456994 (1984-06-01), Segarra
patent: 4488299 (1984-12-01), Fellhauer et al.
patent: 4495642 (1985-01-01), Zellmer
patent: 4517661 (1985-05-01), Graf et al.
patent: 4527249 (1985-07-01), Van Brunt
patent: 4604718 (1986-08-01), Norman et al.
patent: 4635256 (1987-01-01), Herlein
patent: 4644487 (1987-02-01), Smith
patent: 4654851 (1987-03-01), Busby
patent: 4656632 (1987-04-01), Jackson
patent: 4725971 (1988-02-01), Doshi
patent: 4744084 (1988-05-01), Beck
Acken, John M., Delay Modeling in Logic Simulation, 1980 IEEE, pp. 945-947, 05/01/80.
Albrow, Robert, 2-Head Auto-Test System Takes on Complex VLSI, Electronic Design, pp. 79-84, 03/05/81.
Anderson, D. W. et al, Trigger/Latch Technique for Hardware Simulation Programs, IBM Technical Disclosure Bulletin, vol. 24, No. 4, pp. 1866-1868, 09/01/81.
Anderson, Robert E. et al., Processor-Based Tester Goes on Site to Isolate Board Faults Automatically, Electronics, pp. 111-117, 05/11/78.
Anlauff, H. et al., PHPL-A New Computer Hardware Description Language for Modular Description of Logic and Timing, 1979, IEEE, pp. 124-130, 05/01/79.
Axtell, C. R., Reference Testing Techniques for LSI PCB's, 1979 IEEE Test Conference, pp. 358-359, 01/01/79.
Azema, P. et al, Petri Nets as a Common Tool for Design Verification and Hardware Simulation, Laboratoire d'Automatique, pp. 109-116.
Barney, CAE Systems Include Actual IC to Avoid Simulation Obstacle, Electronics, pp. 47-48, 03/08/84.
Barto, R., Szygenda, S. A., A Computer Architecture for Digital Logic Simulation, Electronic Engineering, pp. 35-66, 09/01/80.
Barto, R. L., Szygenda, S. A., Thompson, E. W., Architecture for a Hardware Simulator, 1980 IEEE, pp. 891-893, 01/01/80.
Benson, J. D., Testing Trends for the 1980s, Semiconductor International, pp. 55-58, 01/01/80.
Bissett, S., LSI Tester Gets Microprocessors to Generate Their Own Test Patterns, Electronics, pp. 141-145, 05/25/78.
Blum, A., Use of Independent Error Detection Systems for Field-Replaceable Units, IBM Technical Disclosure Bulletin, vol. 23, No. 4, pp. 1504-1505, 09/01/80.
Brandsma, J. R. et al., The Hardware Simulator: A Tool for Evaluating Computer Systems, IEEE Transactions on Computers, pp. 68-72, 01/01/77.
Brule, J. D. et al., Diagnosis of Equipment Failures, IRE Transactions on Reliability and Control, pp. 23-34, 04/01/60.
Buehler, M. G. et al, Role of Test Chips in Coordinating Logic and Circuit Design and Layout Aids for VLSI, Solid State Technology, pp. 68-74, 09/01/81.
Buehler, M. G. et al, Microelectronic Test Chips and Associated Parametric Testers: Present and Future, National Bureau of Standards and Signetics Corporation, pp. 859-867.
Campbell, J. et al, A New Software System for LSI Testing, Fairchild Systems Technology, pp. 131-134.
Carreno, J. A., Automated Test for a Processor, IBM Technical Disclosure Bulletin, vol. 14, No. 18, pp. 2970-2971, 03/01/72.
Chao, C. C., AC Test Pattern Generation for Sequential Logic, IBM Technical Disclosure Bulletin, pp. 2439-2441, 01/01/74.
Chen, Chung Ho, VLSI Design for Testability, 1979 IEEE Test Conference, pp. 306-309, 09/01/79.
Chrones, C., What's New in Analog Testers, Semiconductor International, pp. 59-70, 09/01/81.
Chrones, Chris, What is New in Memory Testing, Semiconductor International, pp. 67-76, 01/01/81.
Chrones, Chris, LSI Testing Trends, Electronic Packaging and Production, pp. 63-82, 04/01/80.
Crawford, J. D. et al., Unified Hardware Description Language for CAD Programs, 1979 IEEE, pp. 151-154, 05/01/79.
Daisy Systems, Corp., MegaLOGICIAN Physical Modeling Extension (PMX), Brochure, pp. 1-2.
Daisy Systems, Corp., PMX Physical Modeling Extension, Brochure, pp. 1-12.
Davidson, R. P., Some Straightforward Guidelines Help Improve Board Testability, EDN, pp. 127-129, 05/05/79.
Editors, Electronic Engineering, Product Focus: CAE/CAD, Electronic Engineering, pp. 60-73, 07/01/84.
Evangelisti, C. J., Goertzel, G., Ofek, H., Symbolic Simulator for Digital Hardware, IBM Technical Disclosure Bulletin, vol. 21, No. 4, pp. 1736-1739, 09/01/78.
Fee, W. G., Low-Cost LSI Test Solutions, Adar Associates, Inc., pp. 62-63.
Freeman, Physical Modeling Systems Let You Plug VLSI Chips Into Your Workstation's Logic, EDN, pp. 69-73, 11/15/84.
Freund, R. A., Koralek, R. W., A Technique for Testing LSI Closed Loop Networks, 1979 IEEE Test Conference, pp. 317-325, 01/01/79.
Funatsu, S. et al, Easily Testable Design of Large Digital Circuits, NEC Research & Development No. 54, pp. 49-55, 07/01/79.
Gillette, Garry C., Tester Takes on VLSI With 264-K Vectors Behind Its Pins, Electronics, pp. 122-127, 11/03/81.
Gindraux, L. et al, CAE Station's Simulators Tackle 1 Million Gates, Electronic Design, pp. 127-135, 11/10/83.
Grason, J., Design Aids and Hardware Testing of Microprocessor System Circuit Packs, Bell Telephone Laboratories, Inc., pp. 95-99.
Grundmann, J. W., Simulation of Bidirectional Transmission Gates, Missile Systems Group Hughes Aircraft Company, pp. 47-51.
Hellestrand, G. R., MODAL, A System for Digital Hardware Description and Simulation, 1979 IEEE, pp. 131-137, 05/01/79.
Henckels, L. P. et al., Evaluation Criteria for Test Program Generation Systems, 1978 IEEE, pp. 76-78, 02/01/78.
Henckels, Lutz et al., Microprocessor Circuit Board Simulation and Test, Instrumentation Engineering, pp. 17-21.
HHB Systems, CATS Dynamic Hardware Modeler, Brochure, pp. 1-4.
Hirabayashi, K., Watanabe, J., MATIS-Macromodel Timing Simulator for Large Scale Integrated MOS Circuits, 3rd USA-Japan Computer Conference, pp. 457-461, 10/10/78.
Hsu, Frank C., A Comparison Study of the Techniques for Deriving Component Diagnosis for Manufacturing Testing of Cards and Boards, IBM Corporation Systems Products Division, pp. 192-195.
Hughes, John et al., In-Circuit Testing of LSI Components, Electronic Packaging and Production, pp. 79-88, 02/01/81.
Hughes, John et al., In-Circuit Testing of LSI Components, Fairchild Test Systems Group, pp. 263-270.
Huston, R. E., 8086 16-Bit Microprocessor Sentry Program Description, Fairchild, pp. 1-2, 07/24/79.
Huston, R. E., Truth Table Development (Advanced User's Course Materials), Fairchild, pp. 300, 01/01/79.
Huston, R. E., Structure and Method for Testing Microprocessor Central Processing Units, U.S. Patent Application Ser. No. 518,134, pp. 1-40, 10/25/74.
Huston, R. E., Excerpts From Manual, Fairchild, pp. 11.59-11.97.
Huston, R. E., 8086 16-Bit Microprocessor Sentry Functional Pattern Generator Description, Fairchild, pp. 1-300, 07/11/79.
Hutcheson, J. D., Sem

Affiliated with

Also associated with

Rating

Circuit verification accessory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit verification accessory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit verification accessory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1130929