Circuit to syncrhonize the phase of a distributed clock...

Details Circuit to syncrhonize the phase of a distributed clock... Circuit to syncrhonize the phase of a distributed clock...

2006-08-28

2009-11-17

Vo, Don N (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

Reexamination Certificate

active

07620134

ABSTRACT:
A circuit to synchronize the phase of a distributed clock signal to a received clock signal. Embodiments include a control loop comprising a phase interpolator, a clock distribution network, and a data receiver. The clock distribution network provides a sampling clock signal to clock the data receiver. The data receiver receives as its input the received clock signal. Control logic maps a subset of the output samples to a value, and this value is added to the phase introduced by the phase interpolator to provide an updated phase. Embodiments include a second phase interpolator and a second distribution network to clock a second data receiver, where the second data receiver receives the data. The control logic adjusts the second phase interpolator in the same way that it adjusts the phase interpolator. The two data receivers are matched to each other, and the two clock distribution networks are matched to each other. Other embodiments are described and claimed.

REFERENCES:
patent: 6901126 (2005-05-01), Gu
patent: 7325175 (2008-01-01), Momtaz
patent: 7526049 (2009-04-01), Kushiyama
patent: 2004/0170244 (2004-09-01), Cranford et al.
patent: 2005/0238093 (2005-10-01), Payne et al.

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