Circuit to reset a phase locked loop after a loss of lock

Details Circuit to reset a phase locked loop after a loss of lock Circuit to reset a phase locked loop after a loss of lock

2008-09-09

2008-09-09

Pascal, Robert J. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331SDIG002, C331S00100A, C327S157000

Reexamination Certificate

active

11254474

ABSTRACT:
A system and method for generating a reset signal within a Phase Locked Loop (PLL) circuit is described. The reset signal is generated by inputting a reference signal and a lock detect signal into reset circuitry. The reset circuitry within the PLL comprises a series of interconnected latches, or D flip-flops, which are used to create a delay time. The delay time is the amount of time the reset circuit will wait until the reset signal indicates a reset. The reset circuit may also generate a reset signal having a pulse width. The pulse width is determined by the series of interconnected latches. The reset signal may be used to reset a Voltage Controlled Oscillator (VCO) or other circuits within a PLL or it may be used by circuits external to the PLL.

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