Circuit to reduce duty cycle distortion

Details Circuit to reduce duty cycle distortion Circuit to reduce duty cycle distortion

2011-06-28

2011-06-28

Zweizig, Jeffrey S (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

C327S218000

Reexamination Certificate

active

07969224

ABSTRACT:
A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals.

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