Circuit to minimize local clock frequency disturbances when phas

Details Circuit to minimize local clock frequency disturbances when phas Circuit to minimize local clock frequency disturbances when phas

1983-06-23

1985-03-05

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 14, 331 17, 331 27, H03L 710

Patent

active

045034001

ABSTRACT:
A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

REFERENCES:
patent: 4151485 (1979-04-01), La Fratta
patent: 4305045 (1981-12-01), Metz et al.
patent: 4450518 (1984-05-01), Klee

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