Circuit to manage and lower clock inaccuracies of integrated...

Details Circuit to manage and lower clock inaccuracies of integrated... Circuit to manage and lower clock inaccuracies of integrated...

2006-09-05

2006-09-05

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

07102402

ABSTRACT:
A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.

REFERENCES:
patent: 6100735 (2000-08-01), Lu
patent: 6327318 (2001-12-01), Bhullar et al.
patent: 6486716 (2002-11-01), Minami et al.
patent: 6501311 (2002-12-01), Lutkemeyer
patent: 6526109 (2003-02-01), Chang et al.
patent: 6639958 (2003-10-01), Hohler et al.
patent: 6664830 (2003-12-01), Miller

Affiliated with

Also associated with

Rating

Circuit to manage and lower clock inaccuracies of integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit to manage and lower clock inaccuracies of integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit to manage and lower clock inaccuracies of integrated... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3550481