Circuit to eliminate bus contention at chip power up

Details Circuit to eliminate bus contention at chip power up Circuit to eliminate bus contention at chip power up

2002-03-19

2003-05-13

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

06563353

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to the field of an integrated circuit technology. In particular, it relates to a power-on detection circuit at output buffer to ensure output buffer tri-state when high voltage is powered on.
2. Description of the Related Art
In order to prevent leakage and latch up in an ESD device of an IC with plural voltage supply, power-on sequence must be precise in output buffer design. The power-on sequence turns on the high voltage source first and the low voltage source second, but, bus contention results.
FIG. 1A
shows the function block of the I/O circuits and the bus.
FIG. 1B
shows a conventional output buffer
30
. The I/O voltage source VD
33
is powered on, but the core voltage source VDD is not. A PMOS
41
in an output buffer
30
of a circuit
101
is turned on such that a output terminal
40
of the circuit
101
is at high voltage level. A NMOS
40
in a output buffer
30
of a circuit
103
is turned on that an output terminal
40
of the circuit
103
is at low voltage level. Neither a PMOS
41
nor a NMOS
42
is turned on in a output buffer
30
of a circuit
105
such that a output terminal
40
of the circuit
105
is at high-impedance. A short current starts from the circuit
101
to the circuit
103
through a bus
102
. This causes a bus contention among the circuit
101
, the circuit
103
, and the circuit
105
.
The disadvantage of the conventional output buffer is that the state of the output terminal is undetermined when the I/O voltage source is powered on. There are three possible states: high voltage level, low voltage level, or high impedance, creating bus contention. It is necessary to add a power-on detect circuit in a output buffer to ensure the output buffer is at high impedance when I/O voltage source is power-on.
FIG. 2
shows a conventional power-on detect circuit. The gate of a PMOS
62
is coupled to a test signal
67
, the source is coupled to a power supply
75
, and the drain is coupled to a node B. The gate of a NMOS
63
is coupled to a power supply
75
, the source is coupled to a ground, and the drain is coupled to a node B. The input terminals of a NOR gate
65
couple to the test signal
67
and the node B respectively, the output terminal generates reset signal
66
to the reset of a standby flag
61
. The input terminals of AND gate
68
couple to a write signal
69
and node A respectively, and the output terminal of it couples to the set of the standby flag
61
. A standby flag implemented by a R/S latch flip-flop has its output coupled to a bus driver
70
. The control terminal of the bus driver is coupled to a read signal
71
, and the output terminal of it is coupled to the node A.
As shown in
FIG. 3
, the power supply
75
is powered on at time t
1
, the test signal
67
is at low voltage level, such that the PMOS
62
turns on. At time t
2
, the voltage of the power supply increases gradually such that the NMOS turns on and the power-on detect signal
64
(i.e. the node B) is maintained at a low level until the power supply
75
becomes the inversion level. Therefore, the NOR gate
65
is supplied with two low level input signals, so that the NOR gate
65
supplies a high level reset signal
66
to the reset terminal of the standby flag
61
to be reset. At time t
3
, the power supply
75
increases to the inversion level, power-on detecting signal
64
reaches a high level, so that the NOR gate
65
supplies a low level reset signal
66
to the standby flag
61
. The standby flag
61
is set when the AND gate
68
supplies a high logic level on the condition that the write signal
69
is active and the bus
72
is at a high level. An output signal of the standby flag
61
is supplied to the bus
72
through the bus driver
70
when a read signal
71
supplied to the bus
72
becomes active. At time t
4
, the test signal
67
is set be high, so that the PMOS
62
is turned off and the power-on detecting signal
64
is at a low level. During the times t
3
to t
4
, a constant current I
1
flows through the PMOS
62
and the NMOS
63
.
There are two disadvantages in the conventional power-on detect circuit. First, an extra test signal is needed to control the duration of the power-on detecting signal. Second, a constant current flows through the power-on detect circuit when the power-on detecting signal is active.


REFERENCES:
patent: 5929673 (1999-07-01), Haigis et al.
patent: 6329840 (2001-12-01), Moyal

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