Circuit to arbitrate multiple requests for memory access

Details Circuit to arbitrate multiple requests for memory access Circuit to arbitrate multiple requests for memory access

1989-08-08

1991-03-05

Shaw, Gareth D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

364900, 364939, 3649394, G01R 19145

Patent

active

049980300

ABSTRACT:
An asynchronous arbiter circuit processes multiple different address signals that request access to the same memory location during the same memroy cycle. The circuit employs two sets of latches. The circuit recognizes access request signals and refresh request signals. For each type of request signal recognized, an associated first latch stores the value of the request signal received, and outputs a first latch output signal. An associated second latch receives the first output latch signal and translates that into a logic state that is long enough to ascertain whether additional request signals have been inputted into the circuit during the memory cycle. A delay element delays one of the request signals received prior to the signals being inputted into the cycle request logic element. The time period of the delay is determined based upon priority accorded to the particular signals.

REFERENCES:
patent: 4841178 (1989-06-01), Bisson

Affiliated with

Also associated with

Rating

Circuit to arbitrate multiple requests for memory access does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit to arbitrate multiple requests for memory access, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit to arbitrate multiple requests for memory access will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-498764