Excavating
Patent
1996-11-12
1999-07-27
Nguyen, Hoa T.
Excavating
G01R 3128
Patent
active
059302712
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a circuit testing apparatus for testing a circuit such as an IC (semiconductor integrated circuit) of the type having various functional blocks integrated therein or a circuit device of the type having various functional blocks mounted on a board or the like.
BACKGROUND OF THE RELATED ART
FIG. 15 illustrates a general construction of a prior typical circuit testing apparatus (circuit tester) of this kind. The circuit testing apparatus, denoted generally by reference numeral 10, comprises a pattern generator 11, a waveform generator 12 and a logical comparator 13. The waveform generator 12 generates a test pattern signal having a waveform necessary for testing a circuit under test DUT (or circuit to be tested), based on test pattern data included in pattern data which is outputted from the pattern generator 11. The test pattern signal generated by the waveform generator 12 is applied to a group of input terminals of the circuit under test DUT and the response outputs thereof are fed into the logical comparator 13. The logical comparator 13, which is supplied with expected value pattern data included in the pattern data from the pattern generator 11, performs a logical comparison between the expected value pattern data and the response outputs from the circuit under test DUT to sequentially detect whether there is an anti-coincidence between them, and when an anti-coincidence is detected by the logical comparator 13, a failure location of the circuit under test is specified or the like whereby the tested circuit is determined to be a "pass" (conforming circuit) or "failure" (non-conforming circuit).
Various kinds of pattern data including test pattern data, expected value pattern data and the like, which are outputted from the pattern generator 11 are prepared according to the function and scale of a circuit under test DUT, and/or the purpose of the test. Therefore, in case of testing a new kind of circuit device (IC or circuit device mounted on a board), pattern data (such as test pattern data, expected value pattern data, and the like) suitable for such new circuit device must be prepared. It is a general practice in the art to generate the pattern data by using a software, and as matters now stand, the development of the program therefor requires many hands and much time.
With an increase in the integration density of ICs, there is a tendency that an IC has functional blocks such as a memory, central processing means, a logic circuit, and the like integrated in the IC together with other integrated circuits. There are also cases where functional blocks such as a memory, central processing means, a logic circuit, and the like are mounted on a printed circuit board to form a circuit device. Since these functional blocks are interconnected in the IC or circuit board to operate, there is a disadvantage that the functional blocks cannot be tested individually or separately from the outside.
To enable independent testing of each functional block, there has been proposed such a scheme (or solution) that in addition to circuit wiring for actual operations of the functional blocks A, B, C and D, additional circuits RA, RB, RC and RD as well as additional circuits MA, MB, MC and MD are provided in correspondence with the functional blocks A, B, C and D, respectively, as shown in FIG. 16 and then test pattern data can be applied to each of the functional blocks through the additional circuits RA to RD and MA to MD and the corresponding response outputs can be taken out from the respective functional blocks, separately.
Now, this scheme will be described. The additional circuits MA to MD are storage parts that constitute a mode switching register. The outputs of the storage parts MA to MD forming the register are connected to respective mode switching terminals MOD of the corresponding functional blocks A to D as shown. In such construction, when it is desired to test only the functional block A, a serial data of "1, 0, 0, 0", for instance, is inputted to th
REFERENCES:
patent: 4775977 (1988-10-01), Dehara
patent: 5072178 (1991-12-01), Matsumoto
patent: 5390192 (1995-02-01), Fujieda
Siemens, AG; English Translation of DE39 02 835 A1, Aug. 2, 1990, Reference Previously Cited, in German with no Translation, in IDS filed Jun. 1, 1998 .
Advantest Corporation
Nguyen Hoa T.
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