Circuit technique for implementing programmable zeros in high sp

Details Circuit technique for implementing programmable zeros in high sp Circuit technique for implementing programmable zeros in high sp

1995-10-05

1997-07-22

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Unwanted signal suppression

327562, 327103, 330254, 330303, H03F 345

Patent

active

056507470

ABSTRACT:
A circuit technique for implementing programmable zeros in high speed CMOS filters is disclosed. The circuit uses both PMOS and NMOS type transconductance elements to implement a biquad with a real zero and two complex poles. The NMOS transconductance element is biased by the total bias current required by several PMOS transconductance elements and can thus provide larger transconductance as required by the equalization function. Programmability is achieved by dividing the NMOS transconductance elements into a plurality of identical sub-elements that are connected in parallel via digitally programmable switches.

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Umezawa et al., "A 5-V-Only Operation 0.6-.mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1540-1546.

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