Circuit technique for biasing complementary Darlington emitter f

Details Circuit technique for biasing complementary Darlington emitter f Circuit technique for biasing complementary Darlington emitter f

1989-09-28

1991-03-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307313, 307310, 323315, H03K 3013, H03K 1760, H03F 304, G05F 316

Patent

active

050031988

ABSTRACT:
A circuit technique for biasing a complementary NPN-PNP Darlington Emitter Follower Stage without additional biasing resistors or current sources. Four diode-connected transistor are connected in series to provide biasing across the Darlington. Two transistors, one NPN and one PNP, are added with their bases and emitters connected in parallel with the top and bottom diodes, respectively, forming two current mirrors. The collector of the NPN transistor connects to the emitter of the first Darlington NPN transistor. The collector of the PNP transistor connects to the first Darlington PNP transistor. The current mirrors provide equal current to the two first Darlington transistors. These currents are also equal to the current through the four diodes for identically sized transistors.

REFERENCES:
patent: 4945259 (1990-07-01), Anderson
Al Pshaenich, "Driving Inductive Loads", Electronic Design 4, pp. 86-91, Feb. 15, 1977.
IEEE Journal of Solid-State Circuits-A Monolithic Power Op Amp-by Robert J. Widlar and Mineo Yamatake-Apr., 1988-9 pages.
IEEE Journal of Solid-State Circuits, vol. 23, No. 3, Jun. 1988-A Low-Distortion Output Stage with Improved Stability for Monolithic Power Amplifiers by Evert Seevinck, Wim DeJafer, and Piet Buttendijk.

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