Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
2002-03-25
2004-08-03
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
C327S156000, C331S025000
Reexamination Certificate
active
06771096
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a phase-locked loop circuit and, more particularly, to a phase frequency detector within a phase-locked loop circuit that imparts hysteresis into a reset signal to avoid dead zone and other non-linear problems associated with conventional phase frequency detectors.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Phase-locked loop (“PLL”) circuits are typically used for frequency control. As such, PLL circuits are routinely used for data and telecommunications, frequency synthesis, clock recovery, and similar applications. A PLL circuit is often used as a frequency synthesizer, or clock generator. Most clock generators use one or more phase-locked loops to generate one or more different frequencies from one or more reference sources. A reference frequency is usually generated by a reference clock attached to the frequency synthesizer. Ideally, frequency synthesis results in one or more clocking devices that are in phase alignment with the reference clock.
A PLL circuit typically includes four main components: a phase frequency detector (“PFD”), a filter, a voltage controlled oscillator (“VCO”), and a frequency divider. The PLL circuit is arranged to receive a reference clock signal from a reference source. The phase frequency detector is configured to compare the reference clock signal to a feedback clock signal generated by components within the PLL circuit. In particular, the PFD is configured to detect differences in frequency and/or phase between the reference and feedback clock signals, and to generate compensating “up” and “down” signals depending on whether the feedback clock signal is lagging or leading the reference clock signal in frequency or phase. The up/down control signals may be passed through a filter to integrate the control signals into a control voltage, which may be sent to the VCO. The VCO may then convert the voltage information from the up/down control signals into an output signal, which preferably contains frequency and/or phase information. The VCO output signal may be sent back to the PFD via a feedback loop.
In this manner, the PLL circuit is configured to produce a feedback clock signal, which is in phase alignment (i.e. zero phase offset) with the phase of a reference clock signal. If phase alignment is not present, the PFD generates an error signal in the form of the up/down control signals to correct the phase-misalignment. Ideally, the PFD produces an error signal (or, net charge), which is a linear function of the phase offset measured between the reference and feedback signals. As shown in the idealized PFD charge versus phase plot of
FIG. 1
, a linear relationship may exist between the PFD phase offset and the net charge between about +/−2&pgr; (i.e., +/−6.28 radians). A zero net charge may also exist when the phase offset is zero (i.e. when reference and feedback phases are substantially aligned). Thus, the PLL is said to be in frequency and phase “lock” when operating at zero phase offset, or approximately 0.0 Coulombs (Cb), as shown in FIG.
1
.
However, when the two input signals differ in phase by more than about 2&pgr; radians, the output signal may have a negative net charge when the feedback clock signal occurs more often (i.e., when the feedback clock signal has a higher frequency), and a positive net charge when the reference clock signal occurs more often (i.e., when the reference clock signal has a higher frequency). In this manner, the PFD may deliver a negative net charge, or “pump down” pulse, when the feedback clock signal leads the reference clock signal, and a positive net charge, or “pump up” pulse, when the feedback clock signal lags the reference clock signal. Therefore, the error signal output from the PFD may drive the system to a zero phase offset even when the frequencies of the reference and feedback clocks are different.
Many conventional PLL circuits suffer from non-ideal characteristics, which may cause the response of an actual PFD circuit to deviate from the ideal response illustrated in FIG.
1
. Non-ideal characteristics are illustrated in the non-idealized PHD charge versus phase plot of FIG.
2
and may include, for example, decreased linear range and PFD dead zone. The linear range of the PFD may be defined as the region in which a change in phase results in a linear change in net charge delivered to the PLL. Ideally, the linear range of the PFD extends between about +/−2&pgr;, shown as range
10
in FIG.
1
. In practice, however, non-zero gate delays and other timing factors may decrease the actual linear range.
FIG. 2
, for example, illustrates the response of a conventional PFD, which exhibits a decreased linear range extending between approximately +/−1.5&pgr; (represented by range
20
). Decreasing the range in which the PFD is monotonic (i.e. linear) may result in a reduced tracking range and pull-in range, and may also increase lock acquisition time. Thus, it may be important to keep the minimum linear range greater than about +/−&pgr;, due to the inability of the PHD to acquire frequency lock within this range, since the net charge will not correspond to the frequency offset. For example, the PFD may generate the wrong direction (i.e. opposite net charge) for more than half of a +/−2&pgr; range if the linear range is less than +/−&pgr;. Preferably, a practical minimum linear range may be about +/−4&pgr;/3.
Another problem common to conventional PLL circuits, known as the “dead zone,” is illustrated in the non-idealized PFD charge versus phase plot of
FIG. 3
as range
30
. The dead zone includes a narrow frequency band in a region near the phase lock point (i.e. at zero phase offset). Within this narrow phase region, the reference and feedback signals are so close in phase that there may not be enough time for the PFD corrective output pulses to fully switch so that the charge pump can determine the correct phase error value. Once the phase offset drifts out of this phase region, the PFD may start properly correcting again. However, the dead zone tends to reduce the PLL gain at the phase lock point, and thus “deadens” the response.
The PFD circuits described in early literature appear to attribute the dead zone response, such as that shown in
FIG. 3
, to large jitter or wandering phases at the lock point. Jitter is a problem common in almost all high-speed synchronous systems, and may occur when a signal deviates in phase or frequency from that of an ideal clock. Jitter, however, may not be the cause of the dead zone problem. The actual cause of the problem may have been previously unknown due to the common misconception that all PLLs had to live with the effects of the dead zone. In an effort to avoid the dead zone, less than desirable fixes were used to reduce the dead zone effects to more tolerable levels. In one example, a current leaking resistor was added to the low pass filter of the PLL circuit to “pull” the PLL out of the dead zone. Though the addition of a leakage resistor did result in reducing jitter, it also introduced a large and variable phase offset, which made it difficult to achieve zero phase lock. Thus, the inability of conventional PLL circuits to achieve a zero phase offset with the reference clock signal may be one disadvantage of previous methods.
Therefore, it may be desirable to provide an improved PFD having a response that closely follows an ideal phase offset response. As such, it may be desirable to provide an improved PFD that avoids the dead zone problem, while maximizing the extent of the linear range. It may further be desirable to provide an improved PFD that offers lower power and smaller area than currently available PFDs.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by a PFD, alternatively known simply as a detector, which avoids the dead zone problem while maximizing the linear range and minimizi
Meyers Steve
Moyal Nathan
Conley & Rose, P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Nguyen Minh
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