Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2002-04-25
2003-12-02
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S225000
Reexamination Certificate
active
06657472
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a circuit, system and method for avoiding a non-desired output from a latch and, in particular, to a selector circuit that is programmable to select an input to a prioritizer which, based on that input, sets the latch output to avoid a non-desired state regardless of the latching input values.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
A latch is typically understood to be any device that can store information. A popular form of a latch is alternatively known as a “flip-flop.” A latch or flip-flop is designed to produce an output that is stable in one of two logic states. The output logic level will remain until the input to the latch undergoes a change in logic level.
Output from the latch can be at a “true,” “on,” “high,” or “1” logic level or, alternatively, at a “false,” “off,” “low,” or “0” logic level. For convenience in relating relativity to logic level, the former logic level, logical 1, is assumed to be the most positive voltage and the latter logic level, logical 0, represents the most negative voltage value. This relationship is known as positive logic and is used as a convention herein.
There are several types of latches used to store logical 1 or logical 0 logic levels. Latches can be classified as either clocked or non-clocked. If clocked, a clock pulse controls the times at which outputs from the latch can transition. For example, a toggle latch will impart toggling action on the output of the latch during transitions of the clock pulse whenever the toggling input is at a logical 1 logic level. Other forms of latches may not require any clock input whatsoever. For example, a set/reset (SR) latch causes an output from the latch to be set or reset depending on the logic levels of signals placed on the set and reset inputs.
Regardless of whether a latch is clocked or not, there are generally two complimentary outputs produced from a latch. The complimentary outputs are oftentimes referred to as differential outputs, in that while one output is at a logical 1 level, the other output is at a logical 0 level (i.e., complimentary to the former logic level). The complimentary outputs are oftentimes labeled Q and Q′. When one output is at the logical 1 state, the other output is always at a logical 0 state. In this manner, if the latch changes state, then both Q and Q′ change. A latch is considered to be “set” when Q is in a logical 1 state and Q′ is in a logical 0 state. Conversely, the latch is “reset” when Q is in a logical 0 state, and Q′ is in a logical 1 state. Generally, a latch is reset in anticipation of it being subsequently set to store binary information.
A simple example of a non-clocked set/reset (SR) latch is shown in FIG.
1
. In particular,
FIG. 1
illustrates a NAND gate SR latch
10
a
and a NOR gate SR latch
10
b
. Latch
10
a
comprises a pair of cross-connected NAND gates
12
and
14
, while latch
10
b
comprises a pair of cross-connected NOR gates
16
and
18
. Latches
10
each have two inputs labeled S and R (for set and reset) and, therefore, are classified as SR latches. Each latch
10
also has a pair of complimentary outputs labeled Q and “Q bar” (or Q′).
Referring to the truth tables
20
a
and
20
b
, logic levels are shown for outputs Q and Q′ corresponding to inputs S and R. Truth table
20
a
represents the operation of the NAND gate SR latch
10
a
, while truth table
20
b
represents the operation of the NOR gate SR latch
10
b
. Referring to truth table
20
a
, it can be seen that if the S input goes to a logic 0 level, then the latch will go to its set state (Q equals a logic 1 level), and will remain in that state until reset. When the R input goes to a logic 0 level, then the latch will go to its reset state and stay there until it is set again. Thus, an SR latch changes state upon sensing a change in state at the S or R inputs, and stores the results of the change until the opposite input is activated. Truth table
20
b
indicates that the NOR gate SR latch will transition to a set state whenever the S input goes to a logic 1 level, and will transition to a reset state when the R input goes to a logic 1 level.
The set and reset states are noted as “SET” and “RST,” as shown in FIG.
1
. In addition to the set and reset states, two special conditions of interest exist for an SR latch. First, whenever both of the S and R inputs are at a logic 1 level (for the NAND gate embodiment
10
a
) or at a logic 0 level (for the NOR gate embodiment
10
b
) no change is made to the complimentary outputs. This state is noted as a memory (“MEM”) state since the outputs retain their previous logic levels. However, if both of the set and reset inputs are at a logic 0 level (for the NAND gate embodiment
10
a
) or at a logic 1 level (for the NOR gate embodiment
10
b
), then the complimentary output conductors enter the same state: either logic 1 level for the NAND gate latch
10
a
or a logic 0 level for the NOR gate latch
10
b
. Having the same logic level on the complimentary output is not desired and, accordingly, this state is labeled “ND.”
A non-desired output state is to be prevented for at least two reasons. First, the complimentary outputs are generally used elsewhere in the circuit subsystem. That subsystem depends on the Q output being 180° out of phase with the Q′ output. Having the Q and Q′ outputs at the same logic levels could be catastrophic to the operation of any load coupled to receive complimentary inputs. Second, the non-desired state can produce non-deterministic logic levels. For example, if a transistor within logic gate
14
is made having stronger drive outputs than a transistor within NAND gate
12
, then even though the set and reset inputs are at a logic 0 level, the Q output may skew to a differential logic level from that of the Q′ output. This may indicate a set state when, in fact, the set and reset inputs are not in a set condition (e.g., the set input being at a logic 0 level and the reset input being at a logic 1 level for the exemplary NAND gate example).
Therefore, most designers attempt to avoid placing a latch in a non-desired state. However, there may be times when the non-desired state is difficult to avoid and is uncontrollably dependent on the set and reset input conditions. Thus, it would be desirable to introduce an improved SR latch that can avoid a non-desired state regardless of the SR input values. In addition to avoiding a non-desired state, it would be further desirable to provide an improved selector circuit that is easily programmed to force the latch to output complimentary signals regardless of input signals sent to the latch.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved latch including an improved, programmable selector circuit. Preferably, the latch is an SR latch that need not be clocked, and can avoid non-desired states. The latch can be implemented as a quasi-NAND gate or quasi-NOR gate configuration. In addition to the set and reset inputs, the latch receives programmable inputs via the programmable selector circuit. Depending on the logic value of the programmable inputs, the latch can be easily programmed to give priority to the set input, the reset input, or both.
The programmed inputs are fed onto gate conductors or base conductors of respective transistors coupled in series with the transistors that receive the set and reset inputs. The series-connected resistors are also cross-coupled with and parallel to corresponding transistors within a memory or latch cell. The pairs of series-connected transistors can, therefore, form a prioritizer or priority encoder according to one embodiment. The purpose of the memory element is to simply store the complimentary outputs produced by the prioritizer and retain those outputs on the output conductors of the latch. Furthermore, the selector circuit
Meyers Steven C.
Raza S. Babar
Callahan Timothy P.
Conley & Rose, P.C.
Cox Cassandra
Cypress Semiconductor Corp.
Daffer Kevin J.
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