Circuit, system and method for controlling read latency

Details Circuit, system and method for controlling read latency Circuit, system and method for controlling read latency

2007-03-15

2010-02-02

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233110, C365S233120, C365S233500

Reexamination Certificate

active

07656745

ABSTRACT:
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.

REFERENCES:
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patent: 6687185 (2004-02-01), Keeth et al.
patent: 6930955 (2005-08-01), Johnson et al.
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patent: 7119591 (2006-10-01), Lin
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patent: 2006/0182212 (2006-08-01), Hwang et al.
patent: 2008/0144423 (2008-06-01), Kwak

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