Circuit switched switching system

Multiplex communications – Pathfinding or routing – Through a circuit switch

Reexamination Certificate

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Details

C370S411000

Reexamination Certificate

active

06693903

ABSTRACT:

TECHNICAL FIELD
The present invention relates to circuit-switched (versus packet-switched) switching systems and, in particular, to an improved circuit-switched switching system which decomposes the switching function into multiple stages including batching circuits and an improved transposition matrix.
BACKGROUND OF THE INVENTION
Circuit switched switching systems are conventionally employed in telecommunication systems to create a connection between the originating terminal equipment and the destination terminal equipment. In some circumstances, there exists a need to implement versatile, fully non-blocking circuit-switched systems with a minimum of electronic components and a minimum of power consumed. “Non-blocking” refers to the property that if the destination terminal is idle when called, the switch will provide a path from the originating terminal to that destination terminal regardless of what other traffic goes through the switch. Further, transmission of the data through the switch may be adversely affected by transmission errors which occur in the switch due to upset events such as soft errors. Additionally, conventional circuit switched switching systems are limited in the amount of data that may be transferred due to inherent limitations in the switching speed of the switch.
SUMMARY OF THE INVENTION
Aspects of the present invention include methods and devices useful in an improved circuit-switched switching system. In one aspect of the present invention, the switch includes a double buffering memory which allows data to be selectively transmitted through a time multiplex switch in accordance with a dynamically variable scheduling algorithm. The double buffering memory may be configured to read data into the memory in one order and read data out of the memory in another order. In this manner, the data is selectively routed to one of a plurality of output channels. This double buffered memory system allows the switch to be easily reconfigured to accommodate a plurality of data rates.
Another aspect of the invention for increasing the throughput through the switch is to group multiple consecutive samples from the same channel or device as a single unit of information in the switch. For example, the data from a single terminal device may be batched or grouped together for more efficient transmission through the switch. Since such samples are all being routed identically, a grouping, or batching, of samples in this way enables the switch to operate at a significantly slower rate than if specific samples were switched individually.
A further aspect of this invention is that the number of channels and the symbol rate per channel can be changed under software control, such that a wide mix of channel types can be serviced at one time by the switch. Only the aggregate symbol rate, summed across all channels, may be fixed. Further, the number of channels and channel rates can be dynamically changed for a subset of the channels without affecting the operation of other channels currently in use. If the switch is sized and operated to handle the longest frame, i.e., the frame time corresponding to the slowest sampling rate, then faster-rate channels simply amount to reading from the same sample memory multiple times during the designated frame time. In this manner, the switch maintains significant flexibility for operating with a continuing change in the mix of data signals being transmitted through the switch.
Further, in still other aspects of the invention, the data may be protected with an error correction code after it has been grouped together. The grouping of the data makes the use of error correction codes more efficient by requiring fewer bits of error correcting codes per bits of data. The error correction codes are particularly effective where the memories in the switch are vulnerable to soft error upsets, such as in satellite configurations.


REFERENCES:
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patent: 3983330 (1976-09-01), Tongi
patent: 4038497 (1977-07-01), Collins et al.
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patent: 5475679 (1995-12-01), Munter
patent: 5509005 (1996-04-01), Nagamoto
patent: 5555245 (1996-09-01), Alatalo et al.

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