Circuit suitable for use in a carry lookahead adder

Details Circuit suitable for use in a carry lookahead adder Circuit suitable for use in a carry lookahead adder

2007-10-30

2007-10-30

Do, Chat C. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

10059554

ABSTRACT:
An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate, generate, and kill bits corresponding to at least a portion of the first and second operands. The group circuit receives propagate, generate, and kill bits from a plurality of the PGK circuits and produces a set of group propagate, generate, and kill values. The carry generation circuit receives a carry-in bit and the outputs of at least one of the group circuits and generates a carry-out bit representing the carry-out of the corresponding group. The PGK circuits, group circuits, and carry circuits may use CMOS transmission gates in lieu of conventional complementary pass-gate logic (CPL).

REFERENCES:
patent: 5270955 (1993-12-01), Bosshart et al.
patent: 5694350 (1997-12-01), Wolrich et al.
patent: 5719803 (1998-02-01), Naffziger
patent: 6742014 (2004-05-01), Bradley
patent: 6769007 (2004-07-01), Sutherland et al.
patent: 2001/0037349 (2001-11-01), Hayakawa
patent: 2003/0074385 (2003-04-01), Liu
patent: 2004/0078417 (2004-04-01), Dubey et al.

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