Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2007-01-02
2007-01-02
Thai, Luan (Department: 2891)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S112000, C438S123000, C438S124000, C438S127000
Reexamination Certificate
active
10785708
ABSTRACT:
A method is provided to control the height of bump electrodes and increase a clearance between edge sections of a semiconductor chip and lead terminals of a tape substrate. By applying suction to a tape substrate through a suction groove, boundary portions of a semiconductor chip mounting region are drawn into the suction groove, and curved sections are formed in the tape substrate at locations corresponding to edge sections of a semiconductor chip.
REFERENCES:
patent: 6472305 (2002-10-01), Ozaki et al.
patent: 6561743 (2003-05-01), Nakatsu
patent: 2001-035886 (2001-02-01), None
patent: 2001-223306 (2001-08-01), None
patent: 2001-298046 (2001-10-01), None
patent: 2002-009108 (2002-01-01), None
patent: 2002-124536 (2002-04-01), None
Communication from Japanese Patent Office regarding related application.
Harness & Dickey & Pierce P.L.C.
Seiko Epson Corporation
Thai Luan
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