Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2003-03-26
2004-12-14
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S698000, C257S700000
Reexamination Certificate
active
06831357
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a circuit substrate device, on which a pattern conductor has been formed properly, a method for producing the same, a semiconductor device, and a method for producing the same. This application claims priority of Japanese Patent Application No.2002-105549, filed on, 2002, the entirety of which is incorporated by reference herein.
2. Description of Related Art
Recently, there is raised a demand for a technique of mounting functional elements, such as semiconductor chips, on e.g., a substrate, to a high density, for keeping up to the reduction in size and thickness, and to the advanced and diversified functions of electronic equipment. These functional elements are mounted on the substrate in the form of a mold package, such as QFP (Quad Flat Package) or a SOP (Small Outline Package), a package of a smaller size, such as BGA (Ball Grid Array) or CSP (Chip Scale Package), or MCM (multi-chip module), for mounting plural semiconductor chips.
In the mounting configuration for the functional elements, such as BGA, CSP or MCM, a semiconductor chip is mounted on a wiring substrate by pair-chip mounting, and an electrode land is arranged on a surface of the wiring substrate opposite to the surface thereof mounting the wiring substrate. The electrode land is used as a connection terminal to a motherboard.
As a substrate for mounting the semiconductor chip, a wiring substrate of an organic material, such as a glass epoxy substrate or a polyimide substrate, or a wiring substrate of an inorganic material, such as ceramics substrate. In particular, as the wiring substrate of an organic material, used for mounting a semiconductor chip having a large number of connecting terminals, such as connection pins, or used for MCM mounting, a multi-layer wiring substrate
100
, or a so-called FR (flame-retardant) substrate, is used, as shown in FIG.
1
. This multi-layer wiring substrate
100
includes a via-hole
102
, with a diameter on the order of 50 &mgr;m, for interconnecting multi-layered pattern conductors
101
by for example laser processing. With this multi-layer wiring substrate
100
, the line width of the pattern conductor
101
can be as fine as approximately 100 &mgr;m.
However, with the above-described multi-layer wiring substrate
100
, there is raised, in keeping up with the tendency towards an increased number of the semiconductor chips and a decreased pitch between the connection pins, a demand for increasing the density of the pattern conductors
101
on the surface of the multi-layered pattern conductors
101
mounting the semiconductor chip. Since the number of the lines in the semiconductor chip for MCM mounting in near future amounts to several thousands or to several tens of thousands, it is required to raise the density of the pattern conductors
101
further.
If, in the present multi-layer wiring substrate
100
, plural semiconductor chips are connected to a large number of conductor patterns, it becomes necessary to increase the mounting area or to increase the number of layers of the pattern conductors
101
. With the multi-layer wiring substrate
100
, the line length of the pattern conductors
101
in increased, while the number of the via-holes
102
is increased with increasing numbers of the via-holes, with the consequence that the numbers of the C, L and R components in the pattern conductors
101
may be increased to deteriorate electrical characteristics.
Moreover, in producing the multi-layer wiring substrate
100
, the manufacturing process may be complex with the increasing number of the layers of the pattern conductors
101
to increase the production time or to lower the production efficiency.
On the other hand, a wiring substrate of an inorganic material, such as Si substrates or glass substrates, may also be used in place of the multi-layer wiring substrate
100
. Since these Si or glass substrates are superior in surface smoothness and in thermal resistance, pattern conductors may be formed on its mounting surface for semiconductor chips, by employing for example the thin film forming technique, to a finer line width than is possible with the above-described multi-layer wiring substrate
100
.
However, with the Si substrate or the glass substrate, it is difficult to form e.g., via-holes, such that electrode lands, operating as connection terminals for a motherboard, cannot be formed on a surface on the opposite side of the mounting surface for the semiconductor chip, with the consequence that these substrates cannot be used as mounting substrates for the semiconductor chips.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a circuit substrate device and a semiconductor device superior in electrical properties and in high frequency characteristics and which may prohibit the production time and production cost from being increased while prohibiting the production efficiency from being lowered. It is another object of the present invention to provide a method for producing the circuit substrate device and a method for producing a semiconductor device.
In one aspect, the present invention provides a circuit substrate device including a circuit unit having one or more wiring layers each having a pattern conductor formed by a thin film technique, and an insulating layer, the circuit unit also having a land unit, on an uppermost layer of the wiring layer(s), the land unit connecting to the pattern conductor, and a multi-layer wiring substrate including a connecting portion exposed from a major surface thereof. The circuit unit is formed through a release layer on a dummy substrate, having a flattened out surface, while the circuit unit is connected to the major surface of the multi-layer wiring substrate so that the land unit is connected to the connecting portion. The dummy substrate and the release layer are removed by peeling at the release layer to give a structure comprised of the circuit unit formed on the major surface of the multi-layer wiring substrate.
This circuit substrate device is formed by forming a circuit unit on a dummy substrate with a planar surface, with the interposition of a release layer, and by peeling off the dummy substrate and the release layer after the circuit unit having a pattern conductor is attached to the major surface of the multi-layer wiring substrate. With this circuit substrate device, since the waprin or the inundations of the circuit unit along the direction fo thickness may be suppressed, the circuit unit having the fine pattern conductor formed to high accuracy may be formed on the the major surface of the multi-layer wiring substrate.
In still another aspect, the present invention provides a method for producing a circuit substrate device comprising a circuit unit forming step of forming a circuit unit through a release layer, with the circuit unit having one or more wiring layers each having a pattern conductor formed by a thin film technique, and an insulating layer, with the circuit unit also having a land unit, on an uppermost layer of the wiring layer(s), connecting to the pattern conductor, a substrate forming step of forming a multi-layer wiring substrate including a connecting portion exposed from a major surface thereof, a bonding step of connecting the circuit unit to the major surface of the multi-layer wiring substrate for connecting the land unit to the connecting portion, and a removing step of removing the dummy substrate and the release layer by releasing the release layer from the circuit unit.
In this method for producing a circuit substrate device, the circuit substrate device is formed by forming a circuit unit on a dummy substrate with a planar surface, with the interposition of a release layer, and by peeling off the dummy substrate and the release layer after the circuit unit having a pattern conductor is attached to the major surface of the multi-layer wiring substrate. With this circuit substrate device, since the warping or the inundations of the circuit unit along the directi
Asami Hiroshi
Nishitani Yuji
Ogawa Tsuyoshi
Okubora Akihiko
Cao Phat X.
Depke Robert J.
Holland & Knight LLP
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