Circuit structure, semiconductor integrated circuit and path rou

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364489, 364488, G06F 1750

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active

054756111

ABSTRACT:
An interconnection path layout in a circuit structure having terminals arranged in rows, such as a semiconductor integrated circuit. Paths are first assigned to selected obstruction-free terminal pairs to be interconnected, and then bypasses are assigned to the remaining obstruction-existing terminal pairs to be interconnected. This minimizes the occurrence that the terminal pairs are left un-interconnected. Also, longer vertical paths are assigned to selected terminal pairs with priority. This prevents the reserved paths from becoming obstructions to vertical paths which are later assigned to selected terminal pairs.

REFERENCES:
patent: 4613941 (1986-09-01), Smith et al.
patent: 4752887 (1988-06-01), Kuwahara
patent: 4835705 (1989-05-01), Fujino et al.
patent: 4852015 (1989-07-01), Doyle, Jr.
patent: 4855929 (1989-08-01), Nakajima
"Rectilinear Area Routing: A Channel Router Approach" by J. A. Hudson et al., IEEE 1985, pp. 468-471.
"A Hierarchical Routing System for VLSI Including Large Macro" by Hiwatashi et al., IEEE 1986 Cust. Integrated Circuit Conf., pp. 235-238.

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