Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-11-09
2002-03-26
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S738000, C257S728000, C257S737000, C257S723000, C257S778000, C257S528000, C257S531000, C257S777000, C257S668000, C257S700000, C257S701000, C361S760000, C361S764000, C361S765000, C361S767000, C438S381000, C438S238000
Reexamination Certificate
active
06362525
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacturing, and more particularly to a circuit structure including a semiconductor-based integrated circuit coupled to a passive element formed within a grid-array packaging substrate, and a method for forming such a structure.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
A proliferation in the use of devices employing wireless communication, such as wireless telephones, pagers, and personal digital assistants, has led to increased demands on the integrated circuit (IC) technology used in these devices. Many wireless applications involve the use of mixed mode IC's, or circuits which process both analog and digital signals. For example, digital circuitry may be used for data processing functions in a device such as a wireless telephone, while analog circuitry may be used for transmission and/or reception of data over the wireless link. Differences between properties of analog and digital IC's can make mixed mode circuit design and fabrication challenging. As an example, digital IC's fabricated using silicon metal-oxide-semiconductor (MOS) technology typically operate at low power, and most of the circuit components, including logic gates, memory cells, and loads, may be formed using combinations or modifications of MOS transistors. By contrast, analog circuitry used in a transmitter may need to operate at a relatively high power in order to deliver sufficient signal power to the transmitting antenna. Furthermnore, the tuning and filtering circuitry typically used for wireless transmission and reception generally involves the use of passive circuit elements such as inductors and capacitors.
Formation of inductors in IC technology may be particularly challenging. In order for a tuning circuit or filter to efficiently select a desired frequency, an inductor used in the circuit should have a high “quality factor” Q. The quality factor of an element is proportional to the energy stored in the element divided by the energy dissipated or lost in the element per unit time. One way of achieving a high-Q inductor is therefore to minimize energy loss in the inductor. One mechanism of loss in an inductor is resistive heating, which is proportional to the resistance of the inductor. Another way in which energy may be lost from an inductor is by interaction of the electromagnetic field produced when power is applied to the inductor with a lossy medium proximate to the inductor. A lossy medium as used herein has a sufficient concentration of free charge carriers that interaction with an electromagnetic field can cause ohmic losses in the medium. Semiconductors are therefore generally lossy compared to insulators, and a semiconductor such as silicon is lossy compared to a semiconductor having a larger energy gap, such as gallium arsenide.
The loss mechanisms described above can contribute to difficulties in forming a high-Q inductor within a silicon-based IC. One approach to forming an inductor in an IC is to pattern a trace having a spiral geometry within a deposited conductive layer. The resistance of such an inductor is inversely proportional to the cross-sectional area of the patterned trace, which is in turn proportional to the thickness of the conductive layer. A thick conductive layer would therefore be desirable for forming a low-resistance inductor. Use of a conductor having low resistivity would also help to lower the resistance of the inductor. Low resistance is desirable for reducing the above-described resistive losses within the inductor.
However, the thickness of a conductive layer used in IC fabrication is generally limited because of the narrow interconnect feature sizes used in these circuits. For circuits having interconnect feature sizes of 0.25 micron or less, for example, interconnect metal thicknesses may be limited to approximately one micron or less. Thicker conductor layers for these narrow interconnect features could result in difficulty in filling the spaces between patterned interconnects with a dielectric, because deposition into high-aspect-ratio trenches can result in incomplete filling and/or void formation. This metal thickness limitation may be particularly applicable to the case for which copper is used as the interconnect metal. Copper has the lowest resistivity of the interconnect metals in current use, but copper interconnect formation is typically somewhat more involved than formation of interconnects from other metals such as aluminum. Copper interconnects may be formed by a damascene process, in which trenches are formed in a dielectric layer and metal is then deposited to fill the trenches, with excess metal subsequently removed, generally by chemical-mechanical polishing (CMP). A diffusion barrier/adhesion layer is generally deposited within the trenches, followed by a copper seed layer, and then a copper fill layer. The complexity of the copper interconnect formation process may particularly limit the aspect ratio of the trenches and thereby the thickness of the copper traces.
Because a spiral inductor formed within a silicon-based IC as described above would generally be formed in a layer of the circuit which also included interconnect lines for the circuit, the thickness of the inductor trace would be limited to that of the interconnect lines, though the feature size of the inductor trace may not be as small as that for the interconnect lines. Even in a case for which only the inductor were formed on a particular level of the IC, however, the thickness of the inductor metal would be limited by the amount of elevational disparity which can be accommodated by the planarization processes (typically CMP) used in fabricating the circuit.
In addition to the above-described ohmic losses within the inductor resulting from a nonzero resistance of the inductor metal trace, energy in an inductor formed within a silicon-based IC may also be lost through coupling of the inductor's electromagnetic field with the nearby silicon substrate. An inductor formed within a metallization layer of an IC is generally displaced by no more than a few microns from the semiconductor substrate of the IC. The degree of electromagnetic coupling between the field of the inductor and the semiconductor can therefore be substantial. Interaction of the field of the inductor with silicon, which is relatively lossy compared to materials typically used for substrates in high-frequency circuits, may result in conduction in the silicon and thereby loss of energy from the inductor. The proximity of the silicon substrate may therefore also contribute to difficulty in forming a high-Q inductor in a silicon-based IC.
As an alternative to forming a spiral inductor as described above, inductors have also been formed on IC's using wire-bonding wire. This wire has lower resistance than metallization traces, and coupling to the substrate is reduced because such an inductor extends above the surface of the IC and is therefore largely surrounded by air. Because wire-bonding equipment is not designed to produce coils of wire, however, the resulting inductors are generally short loops having relatively low inductance. Furthermore, the reproducibility of the inductor formation is limited, and hand “tweaking” of the inductor may be needed to adjust its inductance value.
Another approach to formation of circuits having high-Q inductors is hybrid circuit fabrication. Hybrid circuit fabrication typically involves mounting IC's and discrete components onto a low-loss substrate, such as a ceramic substrate, and forming interconnections between these elements. In this way, a high-Q discrete inductor may be combined with a silicon-based IC. However, hybrid circuit fabrication requires additional assembly as compared to IC fabrication, and may be more expensive than IC fabrication when large quantities are produced. Hybrid circuits may also be considerably larger than IC
Conley & Rose & Tayon P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
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