Circuit structure for a memory matrix and corresponding manufact

Details Circuit structure for a memory matrix and corresponding manufact Circuit structure for a memory matrix and corresponding manufact

1996-07-29

1997-10-14

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518512, 257316, G11C 1604

Patent

active

056778716

ABSTRACT:
A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit lines, moreover, are gathered into groups or bytes of simultaneously addressable adjacent lines. Each cell in the matrix incorporates a floating gate transistor which is coupled to a control gate, connected to the control gate line, and is connected serially to a selection transistor; also, the cells of each individual byte share their respective source areas, which areas are structurally independent for each byte and are led to a corresponding source addressing line extending along a matrix column.

REFERENCES:
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G. Yaron, et al., "A 16K E.sup.2 PROM Employing New Array Architecture and Designed-In Reliability Features," IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, 1982.

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