Boots – shoes – and leggings
Patent
1989-07-06
1992-04-14
Lall, Parshotam S.
Boots, shoes, and leggings
364488, 371 23, G06F 1560, G06F 1100, G06F 1520
Patent
active
051053748
ABSTRACT:
The circuit simulator stores an information representing a relation between the level transition on an output signal of each element in an object circuit and an input terminal to which a test pattern is applied. When a timing error occurs, an error message outputted based upon the information facilitates to narrow down the range of subjects to be analyzed for seeking the cause of the error, whereby the cause of a timing error can be easily cleared up.
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Jouppi; "Timing Analysis for Nmos VLSI"; 20th Design Automation Conference; 1983.
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AIDA Corp. "Timing Verifier Technical Spec." 1987.
Lall Parshotam S.
Mitsubishi Denki & Kabushiki Kaisha
Ramirez Ellis B.
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