Boots – shoes – and leggings
Patent
1986-12-10
1990-02-06
Williams, Jr., Archie E.
Boots, shoes, and leggings
364221, 3642217, 364264, 3642643, 364265, 364267, 3642672, 3642674, 36426791, 364270, 3642703, 364285, 371 23, G06F 944, G06F 1122, G06F 1126
Patent
active
048992739
ABSTRACT:
A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.
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Kazama Yoshiharu
Kinoshita Yoshiaki
Miyamoto Shunsuke
Miyoshi Masayuki
Nagashima Shigeo
Harrell Robert B.
Hitachi , Ltd.
Williams Jr. Archie E.
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