Boots – shoes – and leggings
Patent
1988-04-28
1990-07-03
Lall, Parshotam S.
Boots, shoes, and leggings
364488, 364489, 364490, 371 23, G06F 1560
Patent
active
049396811
ABSTRACT:
A circuit simulation method and apparatus for simulating the operation of semiconductor devices, including field effect transistors (FETs), on the basis of the mask layout pattern of each semiconductor device. A circuit simulation method is performed by a computer which includes a first step of determining an equivalent circuit of the semiconductor device from the mask layout patterns, and a second step of producing a signal indicative of the operation of the equivalent circuit determined by the first step. The equivalent circuit is determined by extracting resistive area patterns of the FETs and calculating resistance values of FET signal paths to obtain FET equivalent resistances. The resistive area patterns are divided into a series of rectangles which are converted to equivalent resistive elements to then be arranged so that an equivalent resistive value can be calculated.
REFERENCES:
patent: 4656592 (1987-04-01), Spaanenburg et al.
patent: 4791593 (1988-12-01), Hennion
patent: 4803636 (1989-02-01), Nishiyama et al.
patent: 4817012 (1989-03-01), Cali
Yoshio Okamura et al., "Las: Layout Pattern Analysis System with New Approach", Proc. of IEEE ICCC, 1982, pp. 308-311.
J. Yoshida et al., "Panamap-B: A Mask Verification System for Bipolar IC", 18th Design Artomation Conf. Proceedings, Jun., 1981, pp. 690-695.
S. Mori et al., "Resistance Extraction in a Hierarchical IC Artwork Verification System", Proc. of IEEE ICAD, 1985, pp. 196-198.
Steven P. McCormik, "EXCL: A Circuit Extractor for IC Designs", 21st Design Automation Conf. Proceedings, 1984, pp. 616-623.
Johnishi Hirofumi
Maruyama Akihisa
Morioka Toshiyuki
Yajima Akio
Yokomizo Goichi
Hitachi , Ltd.
Lall Parshotam S.
Trans V. N.
LandOfFree
Circuit simulation method for semiconductor device including fie does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit simulation method for semiconductor device including fie, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit simulation method for semiconductor device including fie will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1895837